公开(公告)号：US4809155A

公开(公告)日：1989-02-28

申请号：US33388

申请日：1987-04-02

申请人： Michel L. Costes ,  Gerard Dalboussiere ,  Kenneth J. Barker

发明人： Michel L. Costes ,  Gerard Dalboussiere ,  Kenneth J. Barker

IPC分类号： G06F13/00 ,  G06F13/12 ,  H04L29/04 ,  H04L29/10 ,  G06F3/00

CPC分类号： G06F13/128 ,  G06F13/124

摘要： The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48).The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter.The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.

公开(公告)号：US4695997A

公开(公告)日：1987-09-22

申请号：US744704

申请日：1985-06-14

申请人： Gerard M. Montanari ,  Francis E. Baudelot ,  Michel L. Costes

发明人： Gerard M. Montanari ,  Francis E. Baudelot ,  Michel L. Costes

IPC分类号： H04L1/00 ,  H04J3/14 ,  H04L29/14 ,  H04J1/16 ,  H04M1/24

CPC分类号： H04J3/14

摘要： In a data communication system, a device for performing a wrap test on at least one line without affecting the other lines that transmit and receive data over at least one multiplex link (4) within time slots allocated to a given line within a given frame. During each time slot, a wrap control bit (W) is set by the communication system to a state that indicates either the wrap test mode or the normal mode of operation. Said bit controls a logic circuit (51) to cause data to be sent either over line (4) or to the receive circuit to perform the test, within each time slot.

摘要翻译： 在数据通信系统中，一种用于在至少一条线路上执行卷绕测试而不影响在给定帧内分配给给定线路的时隙内通过至少一个多路复用链路（4）发送和接收数据的其他线路的设备。 在每个时隙期间，通信系统将包装控制位（W）设置为指示卷绕测试模式或正常操作模式的状态。 所述位控制逻辑电路（51），以在每个时隙内通过线路（4）或接收电路发送数据以执行测试。

公开(公告)号：US4630267A

公开(公告)日：1986-12-16

申请号：US680409

申请日：1984-12-10

申请人： Michel L. Costes ,  Gene D. Hodge

发明人： Michel L. Costes ,  Gene D. Hodge

IPC分类号： H04B7/212 ,  H04J3/06

CPC分类号： H04B7/2125

摘要： The disclosed circuit employs a single programmable timer and address decoder which identifies a plurality of bursts received from other stations in a TDMA communications network by means by identifying their origin addresses, and then starts associated timing intervals in the programmable timer for each burst. The instant when the intervals being timed terminate, corresponds approximately to the instant at which the local station should commence its transmission burst. The programmable timer and synchronizer associates each of a plurality of timing intervals with each of the plurality of transmitting stations in the TDMA network, and terminates each respective interval at approximately the same instant in a given local station, thus allowing the time for commencement of the local station's transmission burst to be reliably determined without regard for the participation of any more than one other of the plurality of transmitting stations in the TDMA network. This enables a TDMA communications system to be democratically synchronized in a reliable manner.

摘要翻译： 所公开的电路采用单个可编程定时器和地址解码器，其通过识别其起始地址来标识从TDMA通信网络中的其他站接收的多个突发，然后在每个突发中启动可编程定时器中的相关定时间隔。 当间隔定时终止的时刻大致对应于本地站应该开始传输突发的时刻。 可编程定时器和同步器将多个定时间隔中的每一个与TDMA网络中的多个发射站中的每一个相关联，并且在给定的本地站中大致相同的时刻终止每个相应的间隔，从而允许开始 本地站的传输突发可靠地确定，而不考虑TDMA网络中多个发射站中的多于一个的参与。 这使得TDMA通信系统能够以可靠的方式进行民主地同步。