公开(公告)号：US06314098B1

公开(公告)日：2001-11-06

申请号：US09075843

申请日：1998-05-12

申请人： Michio Masuda ,  Motoo Nishihara ,  Makoto Ogawa

发明人： Michio Masuda ,  Motoo Nishihara ,  Makoto Ogawa

IPC分类号： H04L1256

CPC分类号： H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5645 ,  H04L2012/5658 ,  H04L2012/5667

摘要： In an ATM connectionless communication system for delivering connectionless datagram in the form of sessions through an ATM network, each one of multiple edge units is connected to a user network where quality-of-service (QoS) sessions and No-QoS sessions are mixed. Each of the edge units accommodates an IPv4 packet from the user network into an intermediate frame and accommodates the intermediate frame into ATM cells. The edge units are connected to core units by permanent virtual paths to form a connectionless network. Each of the edge units has a session supervising section for determining whether the IPv4 packet is a QoS session or a No-QoS session, to allocate a control flow number to the IPv4 packet when the IP4 packet is a QoS session.

摘要翻译： 在ATM无连接通信系统中，通过ATM网络以会话的形式发送无连接数据报，多个边缘单元中的每一个连接到混合服务质量（QoS）会话和无QoS会话的用户网络。 每个边缘单元将来自用户网络的IPv4分组容纳到中间帧，并将中间帧容纳到ATM信元中。 边缘单元通过永久虚拟路径连接到核心单元以形成无连接网络。 每个边缘单元具有用于确定IPv4分组是QoS会话还是无QoS会话的会话监控部分，以在IP4分组是QoS会话时向IPv4分组分配控制流号。

公开(公告)号：US06201810B1

公开(公告)日：2001-03-13

申请号：US08910117

申请日：1997-08-13

申请人： Michio Masuda ,  Motoo Nishihara ,  Makoto Ogawa

发明人： Michio Masuda ,  Motoo Nishihara ,  Makoto Ogawa

IPC分类号： H04L1256

CPC分类号： H04L45/04 ,  H04L45/22 ,  H04L45/70

摘要： In a high-speed routing control system, plural path candidates each leading to a destination node are selected on the basis of physical connection information of links connecting respective nodes in a path candidate selection unit 11, and a path candidate containing no congestion-occurring link is specified as the optimum path from the plural path candidates selected by the path candidate selection unit 11 in an optimizing unit 12. Accordingly, even when the destination node is nearer to the self node, the optimum path selection can be performed, and a switching operation to a bypass path can be performed at high speed. In addition, the traffic amount based on topology information can be suppressed, and the large-scaling of the network can be supported.

摘要翻译： 在高速路由选择控制系统中，根据路径候补选择部11中连接各节点的链路的物理连接信息和不包含拥塞发生链路的路径候选，选择各个通向目的地节点的路径候选 被指定为在优化单元12中由路径候选选择单元11选择的多路径候选的最佳路径。因此，即使当目的地节点更靠近自身节点时，也可以执行最佳路径选择，并且切换 可以高速地执行到旁路路径的操作。 此外，可以抑制基于拓扑信息的流量，并且可以支持网络的大规模化。

公开(公告)号：US06330242B1

公开(公告)日：2001-12-11

申请号：US09114135

申请日：1998-07-13

申请人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda ,  Kurenai Murakami

发明人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda ,  Kurenai Murakami

IPC分类号： H04L1228

CPC分类号： H04L45/10 ,  H04L45/34 ,  H04L69/16 ,  H04L69/161 ,  H04L69/168 ,  H04L2012/562 ,  H04L2012/5652 ,  H04L2012/5667 ,  H04Q11/0478

摘要： A loose source routing method is provided to transfer an IP packet from a transmission source gateway to a transfer destination gateway by way of ATM nodes, which are freely designated. At the transmission source gateway, the IP packet given from a user LAN is dissolved into ATM cells containing a BOM cell whose destination address designates the transfer destination gateway. In addition, at least one pseudo BOM cell whose destination address designates an ATM node in the ATM network is added and is located at a top place of a cell stream constructed by the dissolved ATM cells. Thus, the cell stream is transferred from the transmission source gateway to the designated ATM node in accordance with the destination address of the pseudo BOM cell. The designated ATM node discards the pseudo BOM cell so that the original BOM cell is now located at the top place of the cell stream. Then, the cell stream is transferred from the ATM node to the transfer destination gateway in accordance with the destination address of the BOM cell. The transfer destination gateway assembles the ATM cells into the IP packet, which is then sent to a user LAN.

摘要翻译： 提供了一种松散的源路由方法，用于通过自动指定的ATM节点将IP分组从传输源网关传送到传输目的地网关。 在传输源网关，从用户LAN给出的IP分组被解析成包含目的地地址指定传输目的网关的BOM小区的ATM信元。 此外，至少一个其目的地地址指定ATM网络中的ATM节点的伪BOM小区被添加并且位于由解决的ATM信元构成的小区流的顶部。 因此，根据伪BOM小区的目的地地址，将小区流从传输源网关传送到指定的ATM节点。 指定的ATM节点丢弃伪BOM单元，使得原始BOM单元现在位于单元流的顶部。 然后，根据BOM小区的目的地地址，将该小区流从ATM节点传送到传送目的地网关。 传输目的地网关将ATM信元组装成IP包，然后发送给用户LAN。

公开(公告)号：US06208653B1

公开(公告)日：2001-03-27

申请号：US09039556

申请日：1998-03-16

申请人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda

发明人： Makoto Ogawa ,  Motoo Nishihara ,  Michio Masuda

IPC分类号： H04L1228

CPC分类号： H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5648 ,  H04L2012/5667

摘要： The present invention provides a gateway unit which comprises a detecting unit for detecting the congestion from an RM cell from the ATM cell, for discriminating a TCP data gram (TCPDG) from a packet received during the congestion and for acquiring a sequence number of the TCPDG, a sending unit for sending an ACK having a window-controlled value to a transmitting terminal so as to limit a data transmission, and a discarding unit for discarding the packet from the transmitting terminal during the congestion after the confirmation of packet. During the congestion in the ATM network, a pseudo acknowledgment is sent from the gateway unit so as to indicate that the receiving terminal cannot receive data. This restrains the transmission of TCPDG from the transmitting terminal.

摘要翻译： 本发明提供了一种网关单元，其包括检测单元，用于从来自ATM信元的RM信元检测拥塞，用于从拥塞期间接收的分组中识别TCP数据克（TCPDG），并获取TCPDG的序列号 发送单元，用于向发送终端发送具有窗口控制值的ACK以限制数据发送;​​以及丢弃单元，用于在确认分组之后在拥塞期间从发送终端丢弃该分组。 在ATM网络的拥塞期间，从网关单元发送伪确认，以指示接收终端不能接收数据。 这限制了TCPDG从发送终端的传输。

公开(公告)号：US6137798A

公开(公告)日：2000-10-24

申请号：US912188

申请日：1997-08-15

申请人： Motoo Nishihara ,  Michio Masuda ,  Makoto Ogawa

发明人： Motoo Nishihara ,  Michio Masuda ,  Makoto Ogawa

IPC分类号： H04Q3/00 ,  H04L12/46 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/56

CPC分类号： H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/5653 ,  H04L2012/5681

摘要： In a connectionless communication system, a number of interworking units are provided for accommodating local area networks. At the internetworking units, a packet from the local area networks are segmented into cells for transmission to an ATM network. The cells contain a connectionless address designating a designation local area network, a virtual path identifier (VPI) designating a permanent virtual connection, and a virtual channel identifier (VCI) identifying the packet. The ATM network includes a number of cross-connect nodes interconnected by communication links. The cross-connect nodes establish a plurality of permanent virtual connections between the interworking units and the nodes and between the nodes in pairs, receive the cells from the interworking units and route the cells having VCIs of the same value through the permanent virtual connections to a destination interworking unit according to the connectionless address and the VPI contained in the cells. The destination interworking unit assembles the cells having VCIs of the same value into a packet for routine the packet to the destination local area network according to the connectionless address transmitted by the packet.

摘要翻译： 在无连接通信系统中，为了容纳局域网提供多个互通单元。 在互联网络单元中，来自局域网的分组被分割成用于传输到ATM网络的小区。 小区包含指定局域网的无连接地址，指定永久虚拟连接的虚拟路径标识符（VPI）以及标识该分组的虚拟信道标识符（VCI）。 ATM网络包括通过通信链路互连的多个交叉连接节点。 交叉连接节点在互通单元和节点之间以及成对节点之间建立多个永久虚拟连接，从互通单元接收小区，并将具有相同值的VCI的小区通过永久虚拟连接路由到一个 目的地互通单元根据无连接地址和单元中包含的VPI。 目的地互通单元根据分组发送的无连接地址，将具有相同值的VCI的小区组合到用于将分组例程分组到目的地局域网的分组中。

公开(公告)号：US08797711B2

公开(公告)日：2014-08-05

申请号：US12632823

申请日：2009-12-08

申请人： Seiichi Matsumoto ,  Toshiyuki Iwanaga ,  Makoto Ogawa ,  Akihiro Motoki

发明人： Seiichi Matsumoto ,  Toshiyuki Iwanaga ,  Makoto Ogawa ,  Akihiro Motoki

IPC分类号： H01G4/228

CPC分类号： H01G4/30 ,  H01G4/232

摘要： A region where a plating film constituting an external electrode is formed can be accurately controlled in an electronic component in which the external electrode is formed by directly plating a particular region in a surface of a component body. In a component body, a bump is provided in a position in which a region where an external electrode should be formed is partitioned. In a plating process, growth of the plating film constituting the external electrode is substantially stopped or delayed in the bump. As a result, a termination point of the growth of the plating film constituting the external electrode can be accurately controlled in the position of the bump.

摘要翻译： 在形成外部电极的电子部件中，通过直接对构成体的表面的特定区域进行电镀，能够精确地控制形成有构成外部电极的镀膜的区域。 在构成体中，在形成有外部电极的区域被分隔的位置设置凸块。 在电镀工艺中，构成外部电极的镀膜的生长在凸块中基本上停止或延迟。 结果，可以在凸块的位置上精确地控制构成外部电极的镀膜的生长终止点。

公开(公告)号：US08730646B2

公开(公告)日：2014-05-20

申请号：US12466435

申请日：2009-05-15

申请人： Kenichi Kawasaki ,  Shunsuke Takeuchi ,  Akihiro Motoki ,  Makoto Ogawa ,  Toshiyuki Iwanaga

发明人： Kenichi Kawasaki ,  Shunsuke Takeuchi ,  Akihiro Motoki ,  Makoto Ogawa ,  Toshiyuki Iwanaga

IPC分类号： H01G4/008 ,  H01G2/20 ,  H01G4/228

CPC分类号： H01G4/005 ,  H01G4/008 ,  H01G4/232

摘要： A laminated electronic component includes outer terminal electrodes including lower plating films including metal particles having an average size of 0.5 μm or less, the lower plating films being formed by directly plating an outer surface of an electronic component body such that the lower plating films are electrically connected to exposed portions of inner conductors. The outer terminal electrodes may further include upper plating films formed on the lower plating films, the upper plating films being defined by one or more layers. Metal particles defining the upper plating films may have an average size of 0.5 μm or less. The metal particles defining the lower plating films may be Cu particles.

摘要翻译： 层叠电子部件包括外部端子电极，其包括具有平均尺寸为0.5μm以下的金属粒子的下部电镀膜，下部电镀膜通过直接电镀电子部件主体的外表面而形成，使得下部电镀膜为电气 连接到内部导体的暴露部分。 外部端子电极还可以包括形成在下部镀膜上的上部镀膜，上部镀膜由一层或多层限定。 限定上镀膜的金属粒子的平均粒径可以为0.5μm以下。 限定下镀层的金属颗粒可以是Cu颗粒。

公开(公告)号：US08411409B2

公开(公告)日：2013-04-02

申请号：US13161535

申请日：2011-06-16

申请人： Makoto Ogawa ,  Akihiro Motoki ,  Masahito Saruban ,  Toshiyuki Iwanaga ,  Syunsuke Takeuchi ,  Kiyoyasu Sakurada

发明人： Makoto Ogawa ,  Akihiro Motoki ,  Masahito Saruban ,  Toshiyuki Iwanaga ,  Syunsuke Takeuchi ,  Kiyoyasu Sakurada

IPC分类号： H01G4/30

CPC分类号： H01G4/12 ,  H01C1/14 ,  H01G4/005 ,  H01G4/232

摘要： When an external terminal electrode of a ceramic electronic component such as a laminated ceramic capacitor is formed by plating, plating growth may be also caused even in an undesired location. The ceramic surface provided by a component main body is configured to include a high plating growth region of, for example, a barium titanate based ceramic, which exhibits relatively high plating growth, and a low plating growth region of, for example, a calcium zirconate based ceramic, which exhibits relatively low plating growth. The plating film constituting a first layer to define a base for an external terminal electrode is formed in such a way that the growth of a plated deposit deposited with conductive surfaces provided by exposed ends of internal electrodes as starting points is limited so as not to cross over a boundary between the high plating growth region and the low plating growth region toward the low plating growth region.

摘要翻译： 当通过电镀形成层压陶瓷电容器等陶瓷电子部件的外部端子电极时，即使在不希望的位置也可能产生电镀生长。 由组件主体提供的陶瓷表面被构造为包括例如呈现较高镀层生长的例如钛酸钡系陶瓷的高镀层生长区域和例如锆酸锆的低镀层生长区域 其具有相对较低的电镀生长。 构成用于限定外部端子电极的基底的第一层的电镀膜以这样的方式形成，使得以由内部电极的暴露端作为起点设置的导电表面沉积的镀覆沉积物的生长被限制为不交叉 在高电镀生长区域和低电镀生长区域之间的边界朝向低电镀生长区域。

公开(公告)号：US08154848B2

公开(公告)日：2012-04-10

申请号：US12354026

申请日：2009-01-15

申请人： Akihiro Motoki ,  Makoto Ogawa ,  Shunsuke Takeuchi ,  Kenichi Kawasaki

发明人： Akihiro Motoki ,  Makoto Ogawa ,  Shunsuke Takeuchi ,  Kenichi Kawasaki

IPC分类号： H01G4/228 ,  H01G4/06

CPC分类号： H01G4/005 ,  H01G4/008 ,  H01G4/12 ,  H01G4/30

摘要： A multilayer ceramic electronic component includes a laminate including a stack of a plurality of ceramic layers and a plurality of internal electrodes extending along interfaces between the ceramic layers, and a plurality of external electrodes electrically connecting the internal electrodes exposed at surfaces of the laminate. Each external electrode includes a plating layer at least at the portion directly connected to the internal electrodes. The plating layer has a compressive film stress of about 100 MPa or less or a tensile film stress of about 100 MPa or less.

摘要翻译： 多层陶瓷电子部件包括层叠体，其包括多个陶瓷层的叠层和沿着陶瓷层之间的界面延伸的多个内部电极，以及电连接在层叠体的表面露出的内部电极的多个外部电极。 每个外部电极至少包括直接连接到内部电极的部分的镀层。 镀层的压缩应力为约100MPa以下或拉伸膜应力为约100MPa以下。

公开(公告)号：US08018359B2

公开(公告)日：2011-09-13

申请号：US12753784

申请日：2010-04-02

申请人： Makoto Ogawa ,  Tadayuki Okada ,  Kiyoshi Takemura ,  Nobuyoshi Tanaka

发明人： Makoto Ogawa ,  Tadayuki Okada ,  Kiyoshi Takemura ,  Nobuyoshi Tanaka

IPC分类号： H03M7/46

CPC分类号： H03M7/42

摘要： Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.

摘要翻译： 提供了各种实施例，以减少每个分配给多个字符串的多个位长度被转换成多个代码所需的处理时间。 在一个示例性实施例中，响应于多个比特长度的输入，分配每个比特长度的字符串的数量，分配给每个字符串的比特长度以及被分配的一组字符串中的每个字符串的序列号 记录每个位长度。 基于由记录单元记录的串的数量生成多个基本码，每个基准码是用作具有相同比特长度的码的基础的码。 通过分别并行地执行多个字符串来生成多个代码。