-
公开(公告)号：US07643358B2
公开(公告)日：2010-01-05
申请号：US11756936
申请日：2007-06-01
申请人： Michio Nakagawa , Hiroshi Nakamura
发明人： Michio Nakagawa , Hiroshi Nakamura
IPC分类号： G11C7/00
CPC分类号： G11C16/08
摘要： A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.
摘要翻译： 一种非易失性半导体存储器件，其中可以在用于通过使用通常的LVP（低电压P型晶体管）选择性地传输Vpp的传输电路或解码器电路中传输Vpp而不会传输晶体管Vth的电压下降（阈值电压） 以减少生产过程和成本的步骤。 使用LVP（低电压P型晶体管）代替用于传输电路的HVP（高压P型晶体管）。 阈值变为约Vdd的双向二极管插入在栅极和漏极之间。
-
公开(公告)号：US20070278555A1
公开(公告)日：2007-12-06
申请号：US11756936
申请日：2007-06-01
申请人： Michio Nakagawa , Hiroshi Nakamura
发明人： Michio Nakagawa , Hiroshi Nakamura
IPC分类号： H01L29/76
CPC分类号： G11C16/08
摘要： A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.
摘要翻译： 一种非易失性半导体存储器件，其中可以在用于通过使用通常的LVP（低电压P型晶体管）选择性地传输Vpp的传输电路或解码器电路中传输Vpp而不会传输晶体管Vth的电压下降（阈值电压） 以减少生产过程和成本的步骤。 使用LVP（低电压P型晶体管）代替用于传输电路的HVP（高压P型晶体管）。 阈值变为约Vdd的双向二极管插入在栅极和漏极之间。
-
公开(公告)号：US07701773B2
公开(公告)日：2010-04-20
申请号：US12467348
申请日：2009-05-18
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3468
摘要： A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.
摘要翻译： 非易失性半导体存储器件包括多个电可重编程存储器单元，用于将具有对应的高电位电位的多个脉冲信号逐步增加到所述存储单元的电路，以及用于检测所述存储单元的阈值之后的检验电路 应用所述多个脉冲信号。 此外，用于施加所述多个脉冲信号的电路包括用于产生具有第一幅度电压的第一时钟的第一电路和具有高于所述第一幅度电压的第二幅度电压的第二时钟，用于产生所述多个脉冲信号的第二电路 分别基于所述第一时钟或从所述第一电路输入的所述第二时钟的所述脉冲信号具有相应的预定电压;以及第三电路，用于当所述多个脉冲信号时停止所述第一时钟和所述第二时钟的输入到所述第二电路 所述第二电路产生的电压分别达到相应的预定电压。
-
公开(公告)号：US20080192549A1
公开(公告)日：2008-08-14
申请号：US11815387
申请日：2006-02-03
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/3468
摘要： To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.
摘要翻译： 提供一种能够防止写入或擦除操作的降低效率并减少写入时间和擦除时间的非易失性半导体存储器件及其驱动方法。 解决问题的手段非易失性半导体存储装置包括由浮置栅极和层叠在半导体层上的控制栅极形成的电可重写存储单元。 非易失性半导体存储装置向存储单元施加具有逐级高电位的多个阈值波动脉冲，然后检测存储单元的阈值。 当存储单元的阈值不是预定值时，具有逐步高电位的多个阈值波动脉冲从最近施加的阈值波动脉冲的电位在多个阈值波动之中被施加到存储单元 脉冲，添加一定的电位。
-
公开(公告)号：US07190211B2
公开(公告)日：2007-03-13
申请号：US11059255
申请日：2005-02-15
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
摘要翻译： 半导体器件配备有具有一系列多个电荷泵单元的升压电路。 每个单元具有良好的分离型MOS晶体管。 晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。 这允许MOS晶体管的阈值Vth保持在低电平。 这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平） 。 时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。
-
公开(公告)号：US4406087A
公开(公告)日：1983-09-27
申请号：US409536
申请日：1982-08-19
申请人： Hiroshi Asaka , Michio Nakagawa
发明人： Hiroshi Asaka , Michio Nakagawa
CPC分类号： E06B7/28 , E04H9/02 , E05F7/00 , E05Y2900/132
摘要： An aseismatic device for a door comprises a main portion and a roller-bearing plate. The main portion includes a plate capable of being attached to one upper corner of one side door, which is to be closed and locked. The plate is provided with a longitudinally rotatable roller in such a manner that it projects somewhat upwardly and with a laterally rotatable roller in such a manner that it projects somewhat laterally.The roller-bearing plate is capable of being attached to one corner portion of a door frame corresponding to said main portion, and has a pair of planes for bearing said rollers.The main portion and the roller-bearing plate are arranged in such a manner that the rollers are normally not in contact with said bearing planes.
摘要翻译： 用于门的抗震装置包括主要部分和滚子轴承板。 主要部分包括能够被安装到一个侧门的一个上角的板，该板被封闭和锁定。 该板设置有可纵向旋转的滚子，使得其以稍微向外突出的方式稍微向上突出并且具有可横向旋转的滚子。 滚子轴承板能够附接到对应于所述主要部分的门框的一个角部，并且具有用于承载所述辊的一对平面。 主要部分和滚子轴承板以这样的方式设置，使得辊通常不与所述支承平面接触。
-
7.发明授权Multi-level nonvolatile semiconductor memory device capable of discretely controlling a charge storage layer potential based upon accumulated electrons 有权能够基于累积的电子离散地控制电荷存储层电位的多级非易失性半导体存储器件公开(公告)号：US07596020B2
公开(公告)日：2009-09-29
申请号：US11461207
申请日：2006-07-31
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C16/04
CPC分类号： G11C16/102 , G11C11/5621 , G11C2216/08
摘要： A multi-level programmable nonvolatile semiconductor memory device comprises, a charge accumulation layer, a control gate which bias a potential to the charge accumulation layer, wherein the potential of the charge accumulation layer is controlled discretely according to the number of electrons accumulated in the charge accumulation layer.
摘要翻译： 多级可编程非易失性半导体存储器件包括：电荷累积层，将电位偏置到电荷累积层的控制栅极，其中电荷累积层的电位根据在电荷中累积的电子数量离散地被控制 积累层。
-
公开(公告)号：US07545684B2
公开(公告)日：2009-06-09
申请号：US11815387
申请日：2006-02-03
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C5/14
CPC分类号： G11C16/12 , G11C16/3468
摘要： A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.
摘要翻译： 非易失性半导体存储器件包括多个电可重编程存储器单元，用于将具有对应的高电位电位的多个脉冲信号逐步增加到所述存储单元的电路，以及用于检测所述存储单元的阈值之后的检验电路 应用所述多个脉冲信号。 此外，用于施加所述多个脉冲信号的电路包括用于产生具有第一幅度电压的第一时钟的第一电路和具有高于所述第一幅度电压的第二幅度电压的第二时钟，用于产生所述多个脉冲信号的第二电路 分别基于所述第一时钟或从所述第一电路输入的所述第二时钟的所述脉冲信号具有相应的预定电压;以及第三电路，用于当所述多个脉冲信号时停止所述第一时钟和所述第二时钟的输入到所述第二电路 所述第二电路产生的电压分别达到相应的预定电压。
-
公开(公告)号：US20050134362A1
公开(公告)日：2005-06-23
申请号：US11059255
申请日：2005-02-15
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
摘要翻译： 半导体器件配备有具有一系列多个电荷泵单元的升压电路。 每个单元具有良好的分离型MOS晶体管。 晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。 这允许MOS晶体管的阈值Vth保持在低电平。 这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平） 。 时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。
-
公开(公告)号：US06888399B2
公开(公告)日：2005-05-03
申请号：US10358491
申请日：2003-02-04
CPC分类号： G11C5/145 , G05F1/468 , H01L27/0222 , H01L29/94
摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.02 秒)
