公开(公告)号：US20230176738A1

公开(公告)日：2023-06-08

申请号：US17990013

申请日：2022-11-18

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.

公开(公告)号：US20230176866A1

公开(公告)日：2023-06-08

申请号：US17982980

申请日：2022-11-08

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30123

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

公开(公告)号：US12093688B2

公开(公告)日：2024-09-17

申请号：US17989067

申请日：2022-11-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30123

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

公开(公告)号：US20230176867A1

公开(公告)日：2023-06-08

申请号：US17989067

申请日：2022-11-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.