公开(公告)号：US20230176866A1

公开(公告)日：2023-06-08

申请号：US17982980

申请日：2022-11-08

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30123

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

公开(公告)号：US10776292B2

公开(公告)日：2020-09-15

申请号：US16250274

申请日：2019-01-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

IPC: G06F13/12 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14 ,  G06F13/40

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

公开(公告)号：US20190188163A1

公开(公告)日：2019-06-20

申请号：US16250274

申请日：2019-01-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

IPC: G06F13/16 ,  G06F9/38 ,  G06F12/14 ,  G06F9/30 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

公开(公告)号：US12093688B2

公开(公告)日：2024-09-17

申请号：US17989067

申请日：2022-11-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30123

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

公开(公告)号：US20230176867A1

公开(公告)日：2023-06-08

申请号：US17989067

申请日：2022-11-17

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

IPC: G06F9/30

CPC classification number: G06F9/30032

Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

公开(公告)号：US10983931B2

公开(公告)日：2021-04-20

申请号：US15141823

申请日：2016-04-29

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

IPC: G06F13/12 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14 ,  G06F13/40

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

公开(公告)号：US10102050B2

公开(公告)日：2018-10-16

申请号：US15012287

申请日：2016-02-01

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Mike Catherwood ,  Dave Mickey ,  Brian Fall ,  Calum Wilkie ,  Vincent Sheard ,  Alex Dumais

IPC: G06F11/07 ,  G06F11/22 ,  G01R31/28 ,  G06F11/36 ,  G01R31/3177

Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

公开(公告)号：US20160321202A1

公开(公告)日：2016-11-03

申请号：US15141823

申请日：2016-04-29

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/14

CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。