公开(公告)号：US12259705B2

公开(公告)日：2025-03-25

申请号：US17530633

申请日：2021-11-19

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Manivannan Balu ,  Timothy Phoenix ,  Sankar Rangarajan

IPC: G05B19/406

Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

公开(公告)号：US10248521B2

公开(公告)日：2019-04-02

申请号：US15089352

申请日：2016-04-01

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  Brant Ivey ,  Sankar Rangarajan

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/10 ,  G06F11/22

Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

公开(公告)号：US20230393923A1

公开(公告)日：2023-12-07

申请号：US18096163

申请日：2023-01-12

Applicant: Microchip Technology Incorporated

Inventor： Andreas Reiter ,  Yong Yuenyongsgool ,  Stephen Bowling ,  Alex Dumais ,  Justin Oshea ,  Sankar Rangarajan

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0781 ,  G06F11/076

Abstract: A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

公开(公告)号：US20220187788A1

公开(公告)日：2022-06-16

申请号：US17530633

申请日：2021-11-19

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Manivannan Balu ,  Timothy Phoenix ,  Sankar Rangarajan

IPC: G05B19/406

Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

公开(公告)号：US20160292059A1

公开(公告)日：2016-10-06

申请号：US15089352

申请日：2016-04-01

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  Brant Ivey ,  Sankar Rangarajan

IPC: G06F11/263 ,  G06F11/10 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/10 ,  G06F11/2205 ,  G06F11/2215

Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

Abstract translation: 公开了用于硬件验证的运行时纠错码（“ECC”）错误注入方案的系统和方法。 系统和方法包括配置读取路径以内部转发读取数据，以及经由读取故障注入逻辑将至少一个故障位注入转发的读取数据。 系统和方法还可以包括配置写入路径以内部转发写入数据，以及经由写入故障注入逻辑将至少一个故障位注入转发的写入数据。