公开(公告)号：US20240235901A1

公开(公告)日：2024-07-11

申请号：US18417706

申请日：2024-01-19

Applicant: Microchip Technology Incorporated

Inventor： Ravish Soni

IPC: H04L25/03 ,  H03K5/133 ,  H03K17/687

CPC classification number: H04L25/03057 ,  H03K5/133 ,  H03K17/6871

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：US12301389B2

公开(公告)日：2025-05-13

申请号：US18417706

申请日：2024-01-19

Applicant: Microchip Technology Incorporated

Inventor： Ravish Soni

IPC: H04L25/03 ,  H03K5/133 ,  H03K17/687

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：US20220166652A1

公开(公告)日：2022-05-26

申请号：US17456242

申请日：2021-11-23

Applicant: Microchip Technology Incorporated

Inventor： Ravish Soni

IPC: H04L25/03 ,  H03K5/133 ,  H03K17/687

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：US11902057B2

公开(公告)日：2024-02-13

申请号：US17456242

申请日：2021-11-23

Applicant: Microchip Technology Incorporated

Inventor： Ravish Soni

IPC: H04L25/03 ,  H03K5/133 ,  H03K17/687

CPC classification number: H04L25/03057 ,  H03K5/133 ,  H03K17/6871

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：US11621872B2

公开(公告)日：2023-04-04

申请号：US17455506

申请日：2021-11-18

Applicant: Microchip Technology Incorporated

Inventor： Johannes G. Ransijn ,  Ravish Soni

IPC: H04L25/03 ,  H03K3/356 ,  H04L7/00 ,  H04L25/06

Abstract: Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.

公开(公告)号：US20220158875A1

公开(公告)日：2022-05-19

申请号：US17455506

申请日：2021-11-18

Applicant: Microchip Technology Incorporated

Inventor： Johannes G. Ransijn ,  Ravish Soni

IPC: H04L25/03 ,  H04L25/06 ,  H04L7/00 ,  H03K3/356

Abstract: Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.