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公开(公告)号：US11621872B2
公开(公告)日：2023-04-04
申请号：US17455506
申请日：2021-11-18
发明人： Johannes G. Ransijn , Ravish Soni
摘要： Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.
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公开(公告)号：US20220158875A1
公开(公告)日：2022-05-19
申请号：US17455506
申请日：2021-11-18
发明人： Johannes G. Ransijn , Ravish Soni
摘要： Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.
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公开(公告)号：US20240356786A1
公开(公告)日：2024-10-24
申请号：US18640492
申请日：2024-04-19
发明人： Johannes G. Ransijn
CPC分类号： H04L25/03057 , H02M3/07 , H03F3/45475 , H03G5/165 , H04L25/4917
摘要： An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.
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公开(公告)号：US11811568B2
公开(公告)日：2023-11-07
申请号：US17818224
申请日：2022-08-08
发明人： Johannes G. Ransijn
CPC分类号： H04L25/03878 , H04B1/16 , H04B3/14 , H04L25/03057 , H04L25/08 , H04L27/01
摘要： Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.
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公开(公告)号：US20220385504A1
公开(公告)日：2022-12-01
申请号：US17818224
申请日：2022-08-08
发明人： Johannes G. Ransijn
摘要： Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.
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公开(公告)号：US20240356573A1
公开(公告)日：2024-10-24
申请号：US18640491
申请日：2024-04-19
发明人： Johannes G. Ransijn
摘要： An apparatus comprises a discrete-time analog front-end circuit. The discrete-time analog front-end circuit includes a sample and hold circuit, a discrete-time linear equalizer circuit having an input coupled to an output of the sample and hold circuit, and a discrete-time programmable gain amplifier circuit having an input coupled to an output of the discrete-time linear equalizer circuit. The sample and hold circuit is to generate a discrete-time modulated signal at least partially based on a continuous-time modulated signal. The discrete-time linear equalizer circuit is to generate an equalized discrete-time modulated signal at least partially based on the discrete-time modulated signal. The discrete-time programmable gain amplifier circuit is to generate an amplified equalized discrete-time modulated signal at least partially based on the equalized discrete-time modulated signal. The discrete-time analog front-end circuit may include a quantizer circuit having an input coupled to an output of the discrete-time programmable gain amplifier circuit.
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