公开(公告)号：US11443820B2

公开(公告)日：2022-09-13

申请号：US15956526

申请日：2018-04-18

Applicant: Microchip Technology Incorporated

Inventor： Lorenzo Bedarida ,  Simone Bartoli ,  Albert S. Weiner

IPC: G11C29/02 ,  G06F13/28 ,  G11C8/10 ,  G11C16/08 ,  G11C7/24 ,  G11C8/20 ,  G11C29/44 ,  G11C29/38

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

公开(公告)号：US20190228831A1

公开(公告)日：2019-07-25

申请号：US15956526

申请日：2018-04-18

Applicant: Microchip Technology Incorporated

Inventor： Lorenzo Bedarida ,  Simone Bartoli ,  Albert S. Weiner

IPC: G11C29/02 ,  G11C16/08 ,  G11C8/10 ,  G06F13/28

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.