公开(公告)号：US11750188B2

公开(公告)日：2023-09-05

申请号：US17460587

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Bret Addison Johnson ,  Jung-Hwa Choi

IPC: H03K17/687 ,  G06F1/28 ,  G11C11/407

CPC classification number: H03K17/6871 ,  G06F1/28 ,  G11C11/407

Abstract: The systems and methods described herein consider a first channel width of transistors of driver circuitry, where the first channel width may be set to match a second channel width of a power control transistor. A control circuit, for example, may match a second channel width of a set of power control transistors to the first channel width by turning on one or more of the set of power control transistors. Matching the width of the switches of driver circuitry and the width of the set of power control transistors may reduce losses by helping to maintain impedances of the driver circuitry.

公开(公告)号：US20240319879A1

公开(公告)日：2024-09-26

申请号：US18736247

申请日：2024-06-06

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

公开(公告)号：US20230063347A1

公开(公告)日：2023-03-02

申请号：US17461035

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die by a second value.

公开(公告)号：US11127482B1

公开(公告)日：2021-09-21

申请号：US16847181

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Bret Addison Johnson ,  Vijayakrishna J. Vankayala

IPC: G11C29/54 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  G11C29/04

Abstract: As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

公开(公告)号：US12008236B2

公开(公告)日：2024-06-11

申请号：US17461035

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

公开(公告)号：US20230063891A1

公开(公告)日：2023-03-02

申请号：US17460587

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Bret Addison Johnson ,  Jung-Hwa Choi

IPC: H03K17/687 ,  G06F1/28

Abstract: The systems and methods described herein consider a first channel width of transistors of driver circuitry, where the first channel width may be set to match a second channel width of a power control transistor. A control circuit, for example, may match a second channel width of a set of power control transistors to the first channel width by turning on one or more of the set of power control transistors. Matching the width of the switches of driver circuitry and the width of the set of power control transistors may reduce losses by helping to maintain impedances of the driver circuitry.

公开(公告)号：US20210319846A1

公开(公告)日：2021-10-14

申请号：US16847181

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Bret Addison Johnson ,  Vijayakrishna J. Vankayala

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36

Abstract: As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.