公开(公告)号：US20130241608A1

公开(公告)日：2013-09-19

申请号：US13889099

申请日：2013-05-07

Applicant: Micron Technology, Inc.

Inventor： Chang-ki Kwon ,  Eric Booth

IPC: H03L7/00 ,  G06G7/12 ,  H03K17/00

CPC classification number: H03L7/00 ,  G06G7/12 ,  H03K17/00 ,  H03L7/0814

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.

Abstract translation: 本公开涉及与输入缓冲器组合的单位相混合器。 单相混合器具有用于将输出端拉至第一电压的上拉路径。 所述上拉路径具有响应于第一使能信号的第一晶体管和响应于第一时钟信号的串联连接的第二晶体管。 单相混合器具有用于将输出端子向下拉到第二电压的下拉路径。 所述下拉路径具有响应于第二时钟信号的第三晶体管和响应于第二使能信号的串联连接的第四晶体管。 输入缓冲器使第一和第二时钟信号偏移不同的量，以使得能够进行先前的断开操作方法，使得第一电压不连接到第二电压。 单相混频器可以用作更复杂的混频器中的构建块，其可以包括对输入时钟加权的能力以及为某些信号提供前馈路径。 由于抽象的规则，本摘要不应用于解释索赔。

公开(公告)号：US08989692B2

公开(公告)日：2015-03-24

申请号：US13889099

申请日：2013-05-07

Applicant: Micron Technology, Inc.

Inventor： Chang-ki Kwon ,  Eric Booth

IPC: H04B1/26 ,  H03L7/00 ,  H03L7/081 ,  G06G7/12 ,  H03K17/00

CPC classification number: H03L7/00 ,  G06G7/12 ,  H03K17/00 ,  H03L7/0814

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims.