公开(公告)号：US12020030B2

公开(公告)日：2024-06-25

申请号：US17403079

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Bruce Dunlop ,  Gary J. Lucas ,  Edward C. McGlaughlin

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F16/903

CPC classification number: G06F9/3004 ,  G06F9/3836 ,  G06F9/4881 ,  G06F16/90339

Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.

公开(公告)号：US20220222181A1

公开(公告)日：2022-07-14

申请号：US17708677

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Gary J. Lucas ,  Joseph M. Jeddeloh

IPC: G06F12/10

Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.

公开(公告)号：US20210011804A1

公开(公告)日：2021-01-14

申请号：US16510204

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Richard D. Wiita ,  Edward C. McGlaughlin ,  Gary J. Lucas

IPC: G06F11/10 ,  G06F11/14 ,  G11C16/04

Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.

公开(公告)号：US20200104263A1

公开(公告)日：2020-04-02

申请号：US16149961

申请日：2018-10-02

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Gary J. Lucas ,  Joseph M. Jeddeloh

IPC: G06F12/10

Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.

公开(公告)号：US20210064369A1

公开(公告)日：2021-03-04

申请号：US16554332

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Bruce Dunlop ,  Gary J. Lucas ,  Edward C. McGlaughlin

IPC: G06F9/30 ,  G06F9/48 ,  G06F16/903 ,  G06F9/38

Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.

公开(公告)号：US10922221B2

公开(公告)日：2021-02-16

申请号：US15938977

申请日：2018-03-28

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Joseph M. Jeddeloh

IPC: G06F12/02 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C29/52

Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.

公开(公告)号：US20200211645A1

公开(公告)日：2020-07-02

申请号：US16812559

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Samuel E. Bradshaw

IPC: G11C13/00 ,  G06F3/06

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

公开(公告)号：US10586592B1

公开(公告)日：2020-03-10

申请号：US16110758

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Samuel E. Bradshaw

IPC: G06F3/00 ,  G11C13/00 ,  G06F3/06

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

公开(公告)号：US11133061B2

公开(公告)日：2021-09-28

申请号：US16812559

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Samuel E. Bradshaw

IPC: G06F13/00 ,  G11C13/00 ,  G06F3/06

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

公开(公告)号：US20210271548A1

公开(公告)日：2021-09-02

申请号：US17324162

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Richard D. Wiita ,  Edward C. McGlaughlin ,  Gary J. Lucas

IPC: G06F11/10 ,  G06F11/14 ,  G11C16/04

Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.