公开(公告)号：US20250045198A1

公开(公告)日：2025-02-06

申请号：US18678973

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Vishal TANNA ,  Eishan MIRAKHUR ,  Satheesh Babu MUTHUPANDI ,  Rajinikanth PANDURANGAN

IPC: G06F12/02

Abstract: Provided is a memory device, a method and a system that includes a host in communication with a system memory having a driver that creates commands for writing and reading data, and the memory device in communication with the host that includes a memory array including a plurality of memory components, a device attached memory including a submission queue and a completion queue for receiving commands from the driver, and a device controller configure to communicate with the device attached memory, the host and the plurality of memory components, such that the device controller receives an interface or link from the driver indicative of commands being placed into the submission queue, and automatically executes any pending commands therein for completion.

公开(公告)号：US20240319896A1

公开(公告)日：2024-09-26

申请号：US18598767

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Vishal TANNA ,  Krishna SIDDHAREDDY ,  Eishan MIRAKHUR

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.

公开(公告)号：US20240319880A1

公开(公告)日：2024-09-26

申请号：US18598712

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Vishal TANNA ,  Krishna SIDDHAREDDY ,  Eishan MIRAKHUR

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.

公开(公告)号：US20230236742A1

公开(公告)日：2023-07-27

申请号：US17941567

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Rohit SEHGAL ,  Eishan MIRAKHUR ,  Vishal TANNA ,  Rohit SINDHU

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679

Abstract: A memory card, for use with a host system, combines both: (i) non-volatile memory express (NVMe) data storage such as a solid state drive (SSD) with (ii) dynamic random access memory (DRAM) conforming to the computer express link (CXL) protocol. The SSD and CXL DRAM share a common controller. CXL memory requests from the host system are handled according to the CXL.io protocol. NVMe data requests are wrapped into a CXL request packet. The common front end identifies the NVMe data request(s) within the CXL packet, parses the NVMe data request, and routes the request to the NVMe memory. A host operating system software driver intercepts the NVMe memory requests and wraps them into the CXL request packet.