公开(公告)号：US20250132240A1

公开(公告)日：2025-04-24

申请号：US18781338

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE ,  Hong Wan NG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H10B80/00

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, semiconductor device assembly includes a first redistribution layer and a second redistribution layer, a first semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the first redistribution layer, and a second semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the second redistribution layer. The first semiconductor die may have an active surface and a back surface opposite the active surface of the first semiconductor die. The second semiconductor die may have an active surface and a back surface opposite the active surface of the second semiconductor die. The second semiconductor die may be stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die.

公开(公告)号：US20240274580A1

公开(公告)日：2024-08-15

申请号：US18433911

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/4803 ,  H01L23/42 ,  H01L24/32 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/32225 ,  H01L2225/06562 ,  H01L2225/06575

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate. The semiconductor device assembly includes a first semiconductor die above the substrate including an edge and a second semiconductor die in a stacked arrangement above the first semiconductor die. The second semiconductor die comprises an overhang portion extending beyond the edge. The semiconductor device assembly includes a terraced support structure between the overhang portion and the substrate. The terraced support structure may mitigate deflection of the overhang portion during a molding operation to prevent damage to the semiconductor device assembly.

公开(公告)号：US20240145457A1

公开(公告)日：2024-05-02

申请号：US18050099

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE ,  Yeow Chon ONG ,  Wei YU ,  Ling PAN

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73204

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.

公开(公告)号：US20250096046A1

公开(公告)日：2025-03-20

申请号：US18783279

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE ,  Chong Leong GAN ,  Yeow Chon ONG ,  Hong Wan NG

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Implementations described herein relate to techniques and apparatuses related to a structure that may be used for characterizing properties related to an interfacial adhesion strength between an epoxy mold compound and a vertical edge of a semiconductor die included in a semiconductor die package. The techniques and apparatuses may be used to provide a more comprehensive understanding of interfacial adhesion strengths within the semiconductor die package relative to techniques available in semiconductor industry standards.