-
公开(公告)号：US20250168131A1
公开(公告)日：2025-05-22
申请号：US18952670
申请日：2024-11-19
Applicant: Micron Technology, Inc.
Inventor： Leonid Minz , Luigi Pilolli , Gyan Prakash
IPC: H04L49/45 , H04L49/103 , H04L49/25
Abstract: A method includes receiving, by a memory device interface, a signal from a host that includes a header, decoding, by the memory device interface, the header to determine an instruction, selecting, by the memory device interface, a first channel associated with a first memory resource based on the instruction, sending, by the memory device interface, the header to a second channel associated with a second memory resource, and sending, by the memory device interface, subsequent packets of the header to the first channel.
-
公开(公告)号：US20250028373A1
公开(公告)日：2025-01-23
申请号：US18773178
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Leonid Minz , Sivagnanam Parthasarathy
Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.
-
公开(公告)号：US12088301B2
公开(公告)日：2024-09-10
申请号：US17696352
申请日：2022-03-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
-
公开(公告)号：US11747842B1
公开(公告)日：2023-09-05
申请号：US17717599
申请日：2022-04-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Aspects of the present disclosure are directed to multi-referenced power supplies. One method includes sensing each voltage, via a voltage sensor, of plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor, and selecting a feedback voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages.
-
公开(公告)号：US20250117143A1
公开(公告)日：2025-04-10
申请号：US18768914
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F3/06
Abstract: An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.
-
Patent Agency Ranking
公开(公告)号：US20250028595A1
公开(公告)日：2025-01-23
申请号：US18773151
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Leonid Minz , Sivagnanam Parthasarathy
IPC: G06F11/10
Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.
-
公开(公告)号：US12170124B2
公开(公告)日：2024-12-17
申请号：US17692262
申请日：2022-03-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.
-
公开(公告)号：US20240354031A1
公开(公告)日：2024-10-24
申请号：US18630313
申请日：2024-04-09
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0625 , G06F3/0679
Abstract: A method includes reading, from a memory array, a first counter identifier (ID) based on a pointer corresponding to an address location in the memory array in which the first counter ID is stored. The method includes incrementing the pointer to correspond to an address location in the memory array in which a second counter ID is stored and reading, from the memory array the second counter ID based on the pointer corresponding to the address location in the memory array in which the second counter ID is stored.
-
公开(公告)号：US12111781B2
公开(公告)日：2024-10-08
申请号：US18119576
申请日：2023-03-09
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
CPC classification number: G06F13/30 , G06F13/1668
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
-
公开(公告)号：US12044711B2
公开(公告)日：2024-07-23
申请号：US17824479
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
CPC classification number: G01R19/0038 , G11C7/222 , H03K5/14 , H03K3/037
Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.02 seconds)
