公开(公告)号：US20240363153A1

公开(公告)日：2024-10-31

申请号：US18639454

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Gyan Prakash ,  Nidhir Kumar ,  Sandeep Dwivedi

IPC: G11C29/12 ,  G11C29/20

CPC classification number: G11C7/22

Abstract: A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.

公开(公告)号：US20240282730A1

公开(公告)日：2024-08-22

申请号：US18441462

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Kishan Chanumolu ,  Sandeep Dwivedi

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/81 ,  H01L2224/85

Abstract: An apparatus includes a die with a first face, a second face opposite the first face, and a third face located between the first face and the second face, I/O cells coupled to the first face of a die, where the I/O cells are configured to be selectively bonded to a package by wirebonded interconnections at a first pitch or flip-chip interconnections at a second pitch that is larger than the first pitch, and a bond area including decoupling capacitors that is located between each I/O cell and the third face of the die.