公开(公告)号：US20230395153A1

公开(公告)日：2023-12-07

申请号：US17944692

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Tang ,  Eric N. Lee ,  Akira Goda ,  Kishore K. Muchherla ,  Haibo Li ,  Huai-Yuan Tseng

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/08

CPC classification number: G11C16/102 ,  G11C16/14 ,  G11C16/08

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

公开(公告)号：US20250077416A1

公开(公告)日：2025-03-06

申请号：US18781838

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

IPC: G06F12/02

Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

公开(公告)号：US20240256136A1

公开(公告)日：2024-08-01

申请号：US18408836

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Haibo Li ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.