公开(公告)号：US08541836B2

公开(公告)日：2013-09-24

申请号：US13674159

申请日：2012-11-12

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC: H01L29/66

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract translation: 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US20130279277A1

公开(公告)日：2013-10-24

申请号：US13918378

申请日：2013-06-14

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew ,  Jigish D. Trivedi

IPC: G11C7/00

CPC classification number: G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

公开(公告)号：US20130062678A1

公开(公告)日：2013-03-14

申请号：US13674159

申请日：2012-11-12

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

Abstract translation: 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US08971086B2

公开(公告)日：2015-03-03

申请号：US13918378

申请日：2013-06-14

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew ,  Jigish D. Trivedi

IPC: G11C5/06 ,  G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78

CPC classification number: G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.