公开(公告)号：US20180226406A1

公开(公告)日：2018-08-09

申请号：US15942938

申请日：2018-04-02

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Suraj Mathew

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

CPC classification number: H01L27/1052 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10885

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US20130279277A1

公开(公告)日：2013-10-24

申请号：US13918378

申请日：2013-06-14

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew ,  Jigish D. Trivedi

IPC: G11C7/00

CPC classification number: G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

公开(公告)号：US08971086B2

公开(公告)日：2015-03-03

申请号：US13918378

申请日：2013-06-14

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew ,  Jigish D. Trivedi

IPC: G11C5/06 ,  G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78

CPC classification number: G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

公开(公告)号：US09214394B2

公开(公告)日：2015-12-15

申请号：US14470526

申请日：2014-08-27

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/265 ,  H01L21/266 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract translation: 一种制造存储器件的方法包括在衬底中的nMOS区域和pMOS区域。 在nMOS区域内限定第一栅极，并且在pMOS区域中限定第二栅极。 同时限定第一和第二门的一次性间隔物。 通过蚀刻源极/漏极注入和LDD / Halo植入物之间的间隔物，nMOS和pMOS区域被一次一个地选择性地屏蔽，并且使用与每个区域的源/漏植入物相同的掩模进行LDD和Halo植入物。 可以使用nMOS和pMOS区域中的每一个的单个掩模来执行所有晶体管掺杂步骤，包括增强，栅极和阱掺杂。 沟道长度也可以通过在源极/漏极掺杂之前的区域之一中修剪间隔物进行调整。

公开(公告)号：US20190273080A1

公开(公告)日：2019-09-05

申请号：US16414417

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Suraj Mathew

IPC: H01L27/105 ,  H01L21/74 ,  H01L21/768

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US10347634B2

公开(公告)日：2019-07-09

申请号：US15942938

申请日：2018-04-02

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Suraj Mathew

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US20140377919A1

公开(公告)日：2014-12-25

申请号：US14470526

申请日：2014-08-27

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew

IPC: H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/265 ,  H01L21/266 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract translation: 一种制造存储器件的方法包括在衬底中的nMOS区域和pMOS区域。 在nMOS区域内限定第一栅极，并且在pMOS区域中限定第二栅极。 同时限定第一和第二门的一次性间隔物。 通过蚀刻源极/漏极注入和LDD / Halo植入物之间的间隔物，nMOS和pMOS区域被一次一个地选择性地屏蔽，并且使用与每个区域的源/漏植入物相同的掩模进行LDD和Halo植入物。 可以使用nMOS和pMOS区域中的每一个的单个掩模来执行所有晶体管掺杂步骤，包括增强，栅极和阱掺杂。 沟道长度也可以通过在源极/漏极掺杂之前的区域之一中修剪间隔物进行调整。

公开(公告)号：US10930652B2

公开(公告)日：2021-02-23

申请号：US16414417

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Suraj Mathew

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US09852953B2

公开(公告)日：2017-12-26

申请号：US14942693

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/265 ,  H01L21/266 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

公开(公告)号：US20160071775A1

公开(公告)日：2016-03-10

申请号：US14942693

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Suraj Mathew

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/265 ,  H01L21/266 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract translation: 一种制造存储器件的方法包括在衬底中的nMOS区域和pMOS区域。 在nMOS区域内限定第一栅极，并且在pMOS区域中限定第二栅极。 同时限定第一和第二门的一次性间隔物。 通过在源/漏植入物和LDD / Halo植入物之间蚀刻间隔物，nMOS和pMOS区域被选择性地屏蔽，并且使用与每个区域的源/漏植入物相同的掩模进行LDD和Halo植入。 可以使用nMOS和pMOS区域中的每一个的单个掩模来执行所有晶体管掺杂步骤，包括增强，栅极和阱掺杂。 沟道长度也可以通过在源极/漏极掺杂之前的区域之一中修剪间隔物进行调整。