公开(公告)号：US20220011957A1

公开(公告)日：2022-01-13

申请号：US17387308

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Kevin T. Majerus

IPC: G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for quick activate for memory sensing are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a testing procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received activate command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received activate command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US20230114735A1

公开(公告)日：2023-04-13

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US11514968B2

公开(公告)日：2022-11-29

申请号：US16831524

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US20220084577A1

公开(公告)日：2022-03-17

申请号：US17484524

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/08

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US11079949B2

公开(公告)日：2021-08-03

申请号：US16686071

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Kevin T. Majerus

IPC: G11C11/00 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for quick activate for memory sensing are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a testing procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received activate command using a first set of operations having a first duration-rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received activate command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US11749330B2

公开(公告)日：2023-09-05

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US11626150B2

公开(公告)日：2023-04-11

申请号：US17484524

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kevin T. Majerus

IPC: G11C29/50 ,  G11C11/22 ,  G11C29/08

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US11740814B2

公开(公告)日：2023-08-29

申请号：US17387308

申请日：2021-07-28

Applicant: Micron Technology, inc.

Inventor： Kevin T. Majerus

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/22

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2273

Abstract: Methods, systems, and devices for quick activate for memory sensing are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a testing procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received activate command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received activate command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US11139014B2

公开(公告)日：2021-10-05

申请号：US16675065

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/08

Abstract: Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

公开(公告)号：US20210304805A1

公开(公告)日：2021-09-30

申请号：US16831524

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.