公开(公告)号：US20230215495A1

公开(公告)日：2023-07-06

申请号：US17649104

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4087 ,  G11C11/4076

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US20240290379A1

公开(公告)日：2024-08-29

申请号：US18656156

申请日：2024-05-06

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US11749330B2

公开(公告)日：2023-09-05

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US20240381661A1

公开(公告)日：2024-11-14

申请号：US18659356

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Giorgio Servalli ,  Marcello Mariani

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A variety of applications can include apparatus having a memory device with ferroelectric capacitors as storage structures in memory cells. A ferroelectric capacitor can have a bottom electrode, a top electrode, and ferroelectric material, where a leaker electrically couples the bottom electrode to the top electrode. Conductive plates can be positioned on and contacting a different set of the memory cells. The plates can be separated from each other along a direction parallel to an access line to the array, without dummy memory cells between the different sets of memory cells at the edges of the plates. A number of different fabrication options can be implemented to realize a memory array with container structures that can have small container spacing without dummy memory cells at the edges of plate cuts. The different fabrication options can be realized by differences in process related to top electrode formation.

公开(公告)号：US20230114735A1

公开(公告)日：2023-04-13

申请号：US18053305

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US11514968B2

公开(公告)日：2022-11-29

申请号：US16831524

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

公开(公告)号：US20240292630A1

公开(公告)日：2024-08-29

申请号：US18584470

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Marcello Mariani ,  Giorgio Servalli

IPC: H10B53/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

CPC classification number: H10B53/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: A variety of applications can include apparatus having a memory device with ferroelectric capacitors as storage structures in memory cells. The ferroelectric capacitors can be arranged vertically from a region of access transistors of the memory cells with the bottom electrodes of the ferroelectric capacitors arranged above and coupled to the access transistors. The bottom electrodes can be separated from the top electrodes of the ferroelectric capacitors by ferroelectric material. The bottom electrodes of ferroelectric capacitors of adjacent memory cells can be separated by a low-k dielectric material.

公开(公告)号：US12002505B2

公开(公告)日：2024-06-04

申请号：US17649104

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US20210304805A1

公开(公告)日：2021-09-30

申请号：US16831524

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.