公开(公告)号：US09224436B2

公开(公告)日：2015-12-29

申请号：US13902591

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/18 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods for memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了具有单独的全局读写线和/或读出放大器区列选择线的存储器阵列的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。

公开(公告)号：US20140347945A1

公开(公告)日：2014-11-27

申请号：US13902591

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了与具有单独的全局读写线和/或读出放大器区域列选择线的存储器阵列相关的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。

公开(公告)号：US10153007B2

公开(公告)日：2018-12-11

申请号：US14944622

申请日：2015-11-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

公开(公告)号：US11031405B2

公开(公告)日：2021-06-08

申请号：US15802016

申请日：2017-11-02

Applicant: Micron Technology, Inc.

Inventor： Mansour Fardad ,  Harish N. Venkata ,  Jeffrey Koelling

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/12 ,  G11C11/406 ,  G11C29/00 ,  G11C11/4097 ,  G11C5/02

Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

公开(公告)号：US20190131308A1

公开(公告)日：2019-05-02

申请号：US15802016

申请日：2017-11-02

Applicant: Micron Technology, Inc.

Inventor： Mansour Fardad ,  Harish N. Venkata ,  Jeffrey Koelling

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/12

Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

公开(公告)号：US20160071556A1

公开(公告)日：2016-03-10

申请号：US14944622

申请日：2015-11-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了与具有单独的全局读写线和/或读出放大器区域列选择线的存储器阵列相关的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。