公开(公告)号：US10164618B1

公开(公告)日：2018-12-25

申请号：US15857157

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: H03L7/06 ,  H03K5/06 ,  H03K5/08 ,  H03K5/156 ,  G06F1/08

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

公开(公告)号：US10938395B2

公开(公告)日：2021-03-02

申请号：US16809465

申请日：2020-03-04

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  H03L7/081 ,  G11C11/4076 ,  H03K19/20 ,  G11C11/4074 ,  G11C11/408

Abstract: An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.

公开(公告)号：US10797685B2

公开(公告)日：2020-10-06

申请号：US16593865

申请日：2019-10-04

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: H03K5/06 ,  H03K5/08 ,  H03K5/156 ,  G06F1/10 ,  G06F1/30 ,  G06F1/08

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

公开(公告)号：US20200059237A1

公开(公告)日：2020-02-20

申请号：US16566703

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  G11C11/4076 ,  H03L7/081 ,  H03K19/20

Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

公开(公告)号：US10454484B1

公开(公告)日：2019-10-22

申请号：US16103822

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Tyler J. Gomm ,  Michael J. Allen

IPC: H03L7/08 ,  H03L7/081 ,  G11C11/4076 ,  H03K19/20 ,  G11C11/4074 ,  G11C11/408

Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

公开(公告)号：US20190207594A1

公开(公告)日：2019-07-04

申请号：US16184474

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: H03K5/06 ,  H03K5/156 ,  H03K5/08

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

公开(公告)号：US20200099370A1

公开(公告)日：2020-03-26

申请号：US16593865

申请日：2019-10-04

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: H03K5/06 ,  H03K5/08 ,  H03K5/156 ,  G06F1/10 ,  G06F1/30

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

公开(公告)号：US10476488B2

公开(公告)日：2019-11-12

申请号：US16184474

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Dan Shi ,  Fangxing Wei ,  Michael J. Allen

IPC: H03L7/10 ,  H03K5/06 ,  H03K5/08 ,  H03K5/156 ,  G06F1/08

Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.