公开(公告)号：US20220199757A1

公开(公告)日：2022-06-23

申请号：US17125826

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Mikhail A. Treger ,  Albert Liao

IPC: H01L49/02 ,  H01L27/11507 ,  H01L27/11509

Abstract: Some embodiments include a ferroelectric device having a ferroelectric insulative material which includes zinc. Some embodiments include a capacitor having a ferroelectric insulative material between a first electrode and a second electrode. The ferroelectric insulative material includes one or more metal-oxide-containing layers and one or more zinc-containing layers. Some embodiments include a memory array having a first set of first conductive structures and a second set of second conductive structures. The first conductive structures are coupled with driver circuitry, and the second conductive structures are coupled with sensing circuitry. The memory array includes an array of access devices. Each of the access devices is uniquely addressed by one of the first conductive structures in combination with one of the second conductive structures. Ferroelectric capacitors are coupled with the access devices. Each of the ferroelectric capacitors includes ferroelectric insulative material having zinc.

公开(公告)号：US20180204803A1

公开(公告)日：2018-07-19

申请号：US15405711

申请日：2017-01-13

Applicant: Micron Technology, Inc.

Inventor： Gregory C. Herdt ,  Mikhail A. Treger ,  Jin Lu

IPC: H01L23/532 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76856 ,  H01L21/76898 ,  H01L23/481

Abstract: Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.

公开(公告)号：US20240332015A1

公开(公告)日：2024-10-03

申请号：US18427756

申请日：2024-01-30

Applicant: Micron Technology, Inc.

Inventor： Protyush Sahu ,  Mikhail A. Treger ,  Yi Fang Lee ,  Jay S. Brown ,  Shuai Jia ,  Jaidah Mohan ,  Silvia Borsari ,  Richard Beeler ,  Jeffery B. Hull ,  Prashant Raghu

IPC: H01L21/02 ,  H01L21/4763 ,  H10B12/00

CPC classification number: H01L21/02592 ,  H01L21/02598 ,  H01L21/47635 ,  H10B12/02

Abstract: A method of forming an apparatus comprises forming a crystalline semiconductor material comprising one or more of a monocrystalline material and a nanocrystalline material adjacent to active areas of memory cells, forming an amorphous material within portions of the crystalline semiconductor material, forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material, converting a portion of the amorphous material and the metal material to form a metal silicide material adjacent to the crystalline semiconductor material, forming cell contacts over the metal silicide material, and forming a storage node adjacent to the cell contacts. Additional methods and apparatus are also disclosed.

公开(公告)号：US11888019B2

公开(公告)日：2024-01-30

申请号：US17125826

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Mikhail A. Treger ,  Albert Liao

IPC: H01L21/00 ,  H01L49/02 ,  H10B53/30 ,  H10B53/40

CPC classification number: H01L28/60 ,  H10B53/30 ,  H10B53/40

Abstract: Some embodiments include a ferroelectric device having a ferroelectric insulative material which includes zinc. Some embodiments include a capacitor having a ferroelectric insulative material between a first electrode and a second electrode. The ferroelectric insulative material includes one or more metal-oxide-containing layers and one or more zinc-containing layers. Some embodiments include a memory array having a first set of first conductive structures and a second set of second conductive structures. The first conductive structures are coupled with driver circuitry, and the second conductive structures are coupled with sensing circuitry. The memory array includes an array of access devices. Each of the access devices is uniquely addressed by one of the first conductive structures in combination with one of the second conductive structures. Ferroelectric capacitors are coupled with the access devices. Each of the ferroelectric capacitors includes ferroelectric insulative material having zinc.

公开(公告)号：US10403575B2

公开(公告)日：2019-09-03

申请号：US15405711

申请日：2017-01-13

Applicant: Micron Technology, Inc.

Inventor： Gregory C. Herdt ,  Mikhail A. Treger ,  Jin Lu

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

Abstract: Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.