公开(公告)号：US20250061004A1

公开(公告)日：2025-02-20

申请号：US18777251

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Chandana Manjula Linganna ,  Ravi Kiran Gummaluri

IPC: G06F9/50

Abstract: A system can include a host configured to provide requests to, and receive responses from, multiple compute resources. In an example, the compute resources can be distributed on respective accelerator devices that can be configured to communicate with the host using various protocols, such as using compute express link (CXL). A first accelerator device can include a telemetry manager that can receive a queue utilization signal indicative of a volume of transaction request messages or response messages handled by the first accelerator device. The first accelerator device can determine a device loading metric about the first accelerator device based on the queue utilization signal, and can provide a control signal with information about the device loading metric to the host device. The host device can select the first accelerator device or a different device based on the control signal.

公开(公告)号：US20230195659A1

公开(公告)日：2023-06-22

申请号：US17559320

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Robert Walker ,  Laurent Isenegger

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F13/1642 ,  G06F13/1621 ,  G06F13/4221 ,  G06F9/30101

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US12254213B2

公开(公告)日：2025-03-18

申请号：US17558465

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Laurent Isenegger ,  Robert Walker

IPC: G06F3/06 ,  G06F12/02

Abstract: Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US11836096B2

公开(公告)日：2023-12-05

申请号：US17559320

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Robert Walker ,  Laurent Isenegger

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F9/30101 ,  G06F13/1621 ,  G06F13/1642 ,  G06F13/4221

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US20230195657A1

公开(公告)日：2023-06-22

申请号：US17556924

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Chandana Manjula Linganna

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1621 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  G06F13/4221

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to modulate the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request responsive to possession of a credit corresponding to the communication request. In these situations, if the transmitter has exhausted a supply of credits, the transmitter waits until a credit is returned before transmitting another request. The receiver of the requests can manage credit returns based on whether a request queue has space to receive another request. Further, the receiver can delay a credit return based on how many requests are pending at the receiver, even if space is available in the request queue. This delay can prevent an oversupply of requests from developing downstream of the request queue. Latency, for instance, can be improved by managing the presence of requests that are downstream.

公开(公告)号：US11860799B2

公开(公告)日：2024-01-02

申请号：US17556924

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Chandana Manjula Linganna

IPC: G06F13/42 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1621 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  G06F13/4221

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to modulate the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request responsive to possession of a credit corresponding to the communication request. In these situations, if the transmitter has exhausted a supply of credits, the transmitter waits until a credit is returned before transmitting another request. The receiver of the requests can manage credit returns based on whether a request queue has space to receive another request. Further, the receiver can delay a credit return based on how many requests are pending at the receiver, even if space is available in the request queue. This delay can prevent an oversupply of requests from developing downstream of the request queue. Latency, for instance, can be improved by managing the presence of requests that are downstream.

公开(公告)号：US11854600B2

公开(公告)日：2023-12-26

申请号：US17412037

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Laurent Isenegger ,  Kirthi Ravindra Kulkarni

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4078

CPC classification number: G11C11/4076 ,  G11C11/4078 ,  G11C11/4093 ,  G11C11/4096

Abstract: A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

公开(公告)号：US11734203B2

公开(公告)日：2023-08-22

申请号：US17556908

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  Nikesh Agarwal

IPC: G06F13/16 ,  H04L47/10 ,  G06F9/30

CPC classification number: G06F13/1621 ,  G06F9/30043 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  H04L47/39

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to control the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request across an interconnect responsive to possession of a credit. If the transmitter exhausts its credits, the transmitter waits until a credit is returned before transmitting another request. The receiver can manage credit returns based on how many responses are present in a response queue. The receiver can change a rate at which the credit returns are transmitted by changing a size of an interval of responses that are being transmitted, with one credit being returned per interval. This can slow the rate of credit returns while the response queue is relatively more filled. The rate adjustment can decrease latency by reducing an amount of requests or responses that are pooling in backend components.

公开(公告)号：US20230195656A1

公开(公告)日：2023-06-22

申请号：US17556908

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  Nikesh Agarwal

IPC: G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1621 ,  G06F13/1642 ,  G06F13/1668 ,  G06F9/30043 ,  G06F9/30101

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to control the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request across an interconnect responsive to possession of a credit. If the transmitter exhausts its credits, the transmitter waits until a credit is returned before transmitting another request. The receiver can manage credit returns based on how many responses are present in a response queue. The receiver can change a rate at which the credit returns are transmitted by changing a size of an interval of responses that are being transmitted, with one credit being returned per interval. This can slow the rate of credit returns while the response queue is relatively more filled. The rate adjustment can decrease latency by reducing an amount of requests or responses that are pooling in backend components.

公开(公告)号：US20230195368A1

公开(公告)日：2023-06-22

申请号：US17558465

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Laurent Isenegger ,  Robert Walker

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238

Abstract: Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.