公开(公告)号：US09305844B2

公开(公告)日：2016-04-05

申请号：US14626573

申请日：2015-02-19

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L29/76 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US20150162246A1

公开(公告)日：2015-06-11

申请号：US14626573

申请日：2015-02-19

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L21/8234 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US08963156B2

公开(公告)日：2015-02-24

申请号：US13774599

申请日：2013-02-22

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US20140239303A1

公开(公告)日：2014-08-28

申请号：US13774599

申请日：2013-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。