公开(公告)号：US20230170015A1

公开(公告)日：2023-06-01

申请号：US17456968

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Chandra S. Danana ,  Durga P. Panda ,  Luca Laurin ,  Michael J. Irwin ,  Rekha Chithra Thomas ,  Sara Vigano ,  Stephen W. Russell ,  Zia A. Shafi

IPC: G11C13/00 ,  H01L27/24 ,  H01L29/423

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  G11C2213/71

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

公开(公告)号：US11848048B2

公开(公告)日：2023-12-19

申请号：US17456968

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Chandra S. Danana ,  Durga P. Panda ,  Luca Laurin ,  Michael J. Irwin ,  Rekha Chithra Thomas ,  Sara Vigano ,  Stephen W. Russell ,  Zia A. Shafi

IPC: G11C11/00 ,  G11C13/00 ,  H01L29/423 ,  H10B63/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H01L29/4236 ,  H01L29/42376 ,  H10B63/84 ,  G11C2213/71

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.