公开(公告)号：US20240074159A1

公开(公告)日：2024-02-29

申请号：US18236544

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Russell Allen Benson ,  Raghunath Singanamalla

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device with metal digit lines for various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region. In the integrated process flow, material of the metal digit lines can be used as the metal contacts to the transistors in the periphery to the memory array region. In various embodiments, a metal contact can contact a metal gate of a transistor in the periphery or contact a metal barrier region, where the metal barrier region is above and contacting the metal gate and is structured without including polysilicon. Sacrificial polysilicon can be used to protect the gate of the transistor during processing in the memory array region.

公开(公告)号：US20240074166A1

公开(公告)日：2024-02-29

申请号：US18236556

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Raghunath Singanamalla ,  Russell Allen Benson

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/482 ,  H10B12/485

Abstract: A variety of applications can include apparatus having a memory device with metal digit lines coupled to various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region, with a metal silicide formed on the gates of the transistors. The metal silicide for each transistor can be coupled to the metal contact for the transistor. In the integrated process flow, material of the metal digit lines can be used as the metal contact to the transistors in the periphery to the memory array region. The metal silicide can be formed by conversion of polysilicon formed on the memory array region and the periphery to the memory array region in the integrated process flow.

公开(公告)号：US20240074161A1

公开(公告)日：2024-02-29

申请号：US18236579

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Russell Allen Benson ,  Shivani Srivastava ,  Jaydip Guha ,  Raghunath Singanamalla

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.

公开(公告)号：US20240074160A1

公开(公告)日：2024-02-29

申请号：US18236566

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Russell Allen Benson ,  Raghunath Singanamalla ,  Jaydeb Goswami

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.