公开(公告)号：US20220329657A1

公开(公告)日：2022-10-13

申请号：US17719790

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Sharmila Velamur ,  Fatma Arzum Simsek-Ege ,  Shivani Srivastava ,  Marsela Pontoh ,  Lavanya Sriram

IPC: H04L67/125 ,  H04L67/00

Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

公开(公告)号：US20230141716A1

公开(公告)日：2023-05-11

申请号：US17453727

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Hyuck Soo Yang ,  Byung Yoon Kim ,  Yong Mo Yang ,  Shivani Srivastava

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/42364 ,  H01L21/28194 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/10897

Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

公开(公告)号：US20150279694A1

公开(公告)日：2015-10-01

申请号：US14740072

申请日：2015-06-15

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Kunal Shrotri ,  Fawad Ahmed

IPC: H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L21/324 ,  H01L21/02164 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28211 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

Abstract translation: 一些实施方案包括形成二氧化硅的方法，其中使用不大于约1000℃的第一处理温度在硅上形成二氧化硅，并且其中二氧化硅和硅之间的界面利用第二处理温度 其为至少约1050℃。一些实施方案包括形成晶体管的方法，其中形成沟槽以延伸至单晶硅。 利用第一处理温度不大于约1000℃，沿着沟槽内部的多个结晶平面形成二氧化硅，并且利用第二处理温度对二氧化硅和单晶硅之间的界面进行退火 至少约1050℃。晶体管栅极形成在沟槽内，并且在与晶体管栅极相邻的单晶硅内形成一对源/漏区。 一些实施例包括DRAM单元。

公开(公告)号：US20200066730A1

公开(公告)日：2020-02-27

申请号：US16111499

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US12199094B2

公开(公告)日：2025-01-14

申请号：US17453727

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Hyuck Soo Yang ,  Byung Yoon Kim ,  Yong Mo Yang ,  Shivani Srivastava

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H10B12/00

Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

公开(公告)号：US20240074159A1

公开(公告)日：2024-02-29

申请号：US18236544

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Russell Allen Benson ,  Raghunath Singanamalla

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device with metal digit lines for various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region. In the integrated process flow, material of the metal digit lines can be used as the metal contacts to the transistors in the periphery to the memory array region. In various embodiments, a metal contact can contact a metal gate of a transistor in the periphery or contact a metal barrier region, where the metal barrier region is above and contacting the metal gate and is structured without including polysilicon. Sacrificial polysilicon can be used to protect the gate of the transistor during processing in the memory array region.

公开(公告)号：US11323521B1

公开(公告)日：2022-05-03

申请号：US17225204

申请日：2021-04-08

Applicant: Micron Technology, Inc.

Inventor： Sharmila Velamur ,  Fatma Arzum Simsek-Ege ,  Shivani Srivastava ,  Marsela Pontoh ,  Lavanya Sriram

IPC: G06F15/16 ,  H04L67/125 ,  H04L67/00

Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

公开(公告)号：US20240074166A1

公开(公告)日：2024-02-29

申请号：US18236556

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Raghunath Singanamalla ,  Russell Allen Benson

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/482 ,  H10B12/485

Abstract: A variety of applications can include apparatus having a memory device with metal digit lines coupled to various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region, with a metal silicide formed on the gates of the transistors. The metal silicide for each transistor can be coupled to the metal contact for the transistor. In the integrated process flow, material of the metal digit lines can be used as the metal contact to the transistors in the periphery to the memory array region. The metal silicide can be formed by conversion of polysilicon formed on the memory array region and the periphery to the memory array region in the integrated process flow.

公开(公告)号：US20240074161A1

公开(公告)日：2024-02-29

申请号：US18236579

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Russell Allen Benson ,  Shivani Srivastava ,  Jaydip Guha ,  Raghunath Singanamalla

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.

公开(公告)号：US20240074160A1

公开(公告)日：2024-02-29

申请号：US18236566

申请日：2023-08-22

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Russell Allen Benson ,  Raghunath Singanamalla ,  Jaydeb Goswami

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/482

Abstract: A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.