公开(公告)号：US09335372B2

公开(公告)日：2016-05-10

申请号：US13924231

申请日：2013-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott Van De Graaff ,  Tyler Gomm ,  Brandon Roth ,  Eric Becker

IPC: G01R31/317

CPC classification number: G01R31/31725 ,  G01R31/31703

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract translation: 本公开涉及延迟线测试电路和方法。 一方面，集成电路（IC）可以包括多个延迟线，选择电路，延迟比较电路和控制电路。 多个延迟线可以产生多个延迟的时钟信号，并且选择电路可以包括被配置为至少接收多个延迟的时钟信号的多个输入。 选择电路可以基于选择控制信号的状态，在多个输入端接收到的信号之间选择第一输出时钟信号和第二输出时钟信号。 延迟比较电路可以将第一输出时钟信号的延迟与第二输出时钟信号的延迟进行比较，并且可以基于该结果生成诸如通过/失败标志的延迟比较。 控制电路可以产生选择控制信号。

公开(公告)号：US20140375329A1

公开(公告)日：2014-12-25

申请号：US13924231

申请日：2013-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott Van De Graaff ,  Tyler Gomm ,  Brandon Roth ,  Eric Becker

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G01R31/31703

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract translation: 本公开涉及延迟线测试电路和方法。 一方面，集成电路（IC）可以包括多个延迟线，选择电路，延迟比较电路和控制电路。 多个延迟线可以产生多个延迟的时钟信号，并且选择电路可以包括被配置为至少接收多个延迟的时钟信号的多个输入。 选择电路可以基于选择控制信号的状态，在多个输入端接收到的信号之间选择第一输出时钟信号和第二输出时钟信号。 延迟比较电路可以将第一输出时钟信号的延迟与第二输出时钟信号的延迟进行比较，并且可以基于结果生成诸如通过/失败标志的延迟比较。 控制电路可以产生选择控制信号。

公开(公告)号：US20220137827A1

公开(公告)日：2022-05-05

申请号：US17505028

申请日：2021-10-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Scott Van De Graaff ,  Todd Jackson Plum ,  Mark D. Ingram

IPC: G06F3/06

Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.