公开(公告)号：US20140375329A1

公开(公告)日：2014-12-25

申请号：US13924231

申请日：2013-06-21

Applicant: Micron Technology, Inc.

Inventor： Scott Van De Graaff ,  Tyler Gomm ,  Brandon Roth ,  Eric Becker

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G01R31/31703

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract translation: 本公开涉及延迟线测试电路和方法。 一方面，集成电路（IC）可以包括多个延迟线，选择电路，延迟比较电路和控制电路。 多个延迟线可以产生多个延迟的时钟信号，并且选择电路可以包括被配置为至少接收多个延迟的时钟信号的多个输入。 选择电路可以基于选择控制信号的状态，在多个输入端接收到的信号之间选择第一输出时钟信号和第二输出时钟信号。 延迟比较电路可以将第一输出时钟信号的延迟与第二输出时钟信号的延迟进行比较，并且可以基于结果生成诸如通过/失败标志的延迟比较。 控制电路可以产生选择控制信号。

公开(公告)号：US09444469B2

公开(公告)日：2016-09-13

申请号：US14305953

申请日：2014-06-16

Applicant: Micron Technology, Inc.

Inventor： Eric Becker ,  Brandon Roth ,  Scott Schafer

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H03L7/091 ,  H03L7/095 ,  G11C11/4063

CPC classification number: H03L7/0814 ,  G11C11/4063 ,  H03L7/087 ,  H03L7/091 ,  H03L7/095

Abstract: Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.

Abstract translation: 本文公开的装置，系统和方法可以初始化延迟锁定环（DLL）或锁相环（PLL）以实现锁定状态，然后可以启动静态操作模式。 可以通过断开与DLL或PLL相关联的反馈回路来实现静态操作，以防止与DLL相关联的可变延迟线和/或与PLL相关联的可变频率振荡器的更新。 因此，与DLL或PLL相关联的输出时钟相位可以在DLL初始化时段之后保持基本上恒定。 公开并要求保护附加实施例。

公开(公告)号：US09335372B2

公开(公告)日：2016-05-10

申请号：US13924231

申请日：2013-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott Van De Graaff ,  Tyler Gomm ,  Brandon Roth ,  Eric Becker

IPC: G01R31/317

CPC classification number: G01R31/31725 ,  G01R31/31703

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract translation: 本公开涉及延迟线测试电路和方法。 一方面，集成电路（IC）可以包括多个延迟线，选择电路，延迟比较电路和控制电路。 多个延迟线可以产生多个延迟的时钟信号，并且选择电路可以包括被配置为至少接收多个延迟的时钟信号的多个输入。 选择电路可以基于选择控制信号的状态，在多个输入端接收到的信号之间选择第一输出时钟信号和第二输出时钟信号。 延迟比较电路可以将第一输出时钟信号的延迟与第二输出时钟信号的延迟进行比较，并且可以基于该结果生成诸如通过/失败标志的延迟比较。 控制电路可以产生选择控制信号。

公开(公告)号：US09153303B2

公开(公告)日：2015-10-06

申请号：US14031470

申请日：2013-09-19

Applicant: Micron Technology, Inc.

Inventor： Eric Becker

IPC: G11C7/10 ,  G11C7/22 ,  H03L7/06 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  H03L7/06

Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.

Abstract translation: 公开了诸如包括产生备用时钟的振荡器电路的装置和方法。 复用电路可以耦合到备用时钟和输入时钟。 交替时钟具有比输入时钟更精确的占空比。 时钟路径可以耦合到多路复用电路的输出。 在测试模式期间，更准确的备用时钟可以耦合到时钟路径。

公开(公告)号：US20150078101A1

公开(公告)日：2015-03-19

申请号：US14031470

申请日：2013-09-19

Applicant: Micron Technology, Inc

Inventor： Eric Becker

IPC: G11C7/22 ,  H03L7/06

CPC classification number: G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  H03L7/06

Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.

Abstract translation: 公开了诸如包括产生备用时钟的振荡器电路的装置和方法。 复用电路可以耦合到备用时钟和输入时钟。 交替时钟具有比输入时钟更精确的占空比。 时钟路径可以耦合到多路复用电路的输出。 在测试模式期间，更准确的备用时钟可以耦合到时钟路径。

公开(公告)号：US20140292389A1

公开(公告)日：2014-10-02

申请号：US14305953

申请日：2014-06-16

Applicant: Micron Technology, Inc.

Inventor： Eric Becker ,  Brandon Roth ,  Scott Schafer

IPC: H03L7/081 ,  G11C11/4063 ,  H03L7/095 ,  H03L7/087 ,  H03L7/091

CPC classification number: H03L7/0814 ,  G11C11/4063 ,  H03L7/087 ,  H03L7/091 ,  H03L7/095

Abstract: Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.

Abstract translation: 本文公开的装置，系统和方法可以初始化延迟锁定环（DLL）或锁相环（PLL）以实现锁定状态，然后可以启动静态操作模式。 可以通过断开与DLL或PLL相关联的反馈回路来实现静态操作，以防止与DLL相关联的可变延迟线和/或与PLL相关联的可变频率振荡器的更新。 因此，与DLL或PLL相关联的输出时钟相位可以在DLL初始化时段之后保持基本上恒定。 公开并要求保护附加实施例。