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    Semiconductor Constructions
    5.
    发明申请
    Semiconductor Constructions 有权
    半导体建筑

    公开(公告)号：US20150054164A1

    公开(公告)日：2015-02-26

    申请号：US13975722

    申请日：2013-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Gowrisankar Damarla ,  Robert J. Hanson ,  Jin Lu ,  Shyam Ramalingam

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

    Abstract translation: 一些实施例包括具有在交叉点处彼此相交的第一和第二导电线的半导体结构。 第一线主要具有第一宽度，并且具有直接相对于第二线并且在第二线的相对侧彼此变窄的区域。 导电触头沿着第一线并且直接电耦合到第一线，并且一个导电触头直接抵靠该交叉。 一些实施例包括形成相交线材料的方法。 形成第一和第二沟槽，并在相交处相互交叉。 第一沟槽主要具有第一宽度，并且将区域直接靠在第二沟槽和第二沟槽的相对侧上彼此变窄。 材料沉积在第一和第二沟槽内，以基本上完​​全填充第一和第二沟槽。

    CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS
    8.
    发明申请
    CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS 有权
    包含负离子热膨胀材料的导电互连结构和相关的综合，装置和方法

    公开(公告)号：US20150340282A1

    公开(公告)日：2015-11-26

    申请号：US14815560

    申请日：2015-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

    IPC: H01L21/768 ,  H01L21/288

    CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

    Abstract translation: 本文公开了具有并入负扩张（NTE）材料的互连的半导体器件。 在一个实施例中，半导体器件包括具有至少部分延伸穿过衬底的开口的衬底。 具有正的热膨胀系数（CTE）的导电材料部分地填充开口。 具有负CTE的负热膨胀（NTE）也部分填充开口。 在一个实施例中，导电材料包括铜，NTE材料包括钨酸锆。

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