公开(公告)号：US11295812B2

公开(公告)日：2022-04-05

申请号：US16453772

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00 ,  H01L27/10

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US10438661B2

公开(公告)日：2019-10-08

申请号：US15162420

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00 ,  H01L27/10

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US20140362633A1

公开(公告)日：2014-12-11

申请号：US13914415

申请日：2013-06-10

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract translation: 描述了存储器件和存储器操作方法。 一个示例性存储器系统包括公共导体和与公共导体耦合的多个存储单元。 存储器系统另外包括访问电路，其被配置为在第一和第二时刻之间的多个不同的时刻将不同的存储单元提供给多个不同的存储器状态之一。 访问电路还被配置为在第一和第二时刻之间将公共导体保持在对应于一个存储器状态的电压电位，以将存储器单元提供到一个存储器状态。

公开(公告)号：US20190311767A1

公开(公告)日：2019-10-10

申请号：US16437997

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

公开(公告)号：US20190318782A1

公开(公告)日：2019-10-17

申请号：US16453772

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US20160203861A1

公开(公告)日：2016-07-14

申请号：US15076451

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitigawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0002 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract translation: 描述了存储器单元，存储器系统和方法。 在一个实施例中，存储单元包括电极和存储元件，并且第一导电结构形成在电介质材料内，由于施加在电极上的第一极性的第一电压，从而提供低电阻状态的存储元件 。 另外，由于与第一极性相反的第二极性的第二电压被施加在电极两端，所以第一导电结构从提供存储元件的电介质材料中移除到高电阻状态。 作为第二极性的第三电压的结果，在提供存储元件处于低电阻状态的电介质材料中形成永久且不可逆的导电结构，并且与施加在电极上的第二电压相比具有增加的电位。

公开(公告)号：US20140268992A1

公开(公告)日：2014-09-18

申请号：US13837911

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitigawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0002 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract translation: 描述了存储器单元，存储器系统和方法。 在一个实施例中，存储单元包括电极和存储元件，并且第一导电结构形成在电介质材料内，由于施加在电极上的第一极性的第一电压，从而提供低电阻状态的存储元件 。 另外，由于与第一极性相反的第二极性的第二电压被施加在电极两端，所以第一导电结构从提供存储元件的电介质材料中移除到高电阻状态。 作为第二极性的第三电压的结果，在提供存储元件处于低电阻状态的电介质材料中形成永久且不可逆的导电结构，并且与施加在电极上的第二电压相比具有增加的电位。

公开(公告)号：US10395731B2

公开(公告)日：2019-08-27

申请号：US15858201

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino ,  D. V. Nirmal Ramaswamy

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

公开(公告)号：US20190080759A1

公开(公告)日：2019-03-14

申请号：US16189387

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US20160267978A1

公开(公告)日：2016-09-15

申请号：US15162420

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract translation: 描述了存储器件和存储器操作方法。 一个示例性存储器系统包括公共导体和与公共导体耦合的多个存储单元。 存储器系统另外包括访问电路，其被配置为在第一和第二时刻之间的多个不同的时刻将不同的存储单元提供给多个不同的存储器状态之一。 访问电路还被配置为在第一和第二时刻之间将公共导体保持在对应于一个存储器状态的电压电位，以将存储器单元提供到一个存储器状态。