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公开(公告)号：US11615826B1
公开(公告)日：2023-03-28
申请号：US17468044
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Chih-Kuo Kao , Yueh-Hung Chen , Jiangli Zhu
Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising: responsive to receiving a memory access command, determining that the memory access command is a dual-address command comprising a source address and a destination address; generating a first content addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing, to the memory device, the read command associated with the first CAM entry.
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公开(公告)号：US20230070078A1
公开(公告)日：2023-03-09
申请号：US17940751
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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公开(公告)号：US20230072501A1
公开(公告)日：2023-03-09
申请号：US17468044
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Chih-Kuo Kao , Yueh-Hung Chen , Jiangli Zhu
Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising: responsive to receiving a memory access command, determining that the memory access command is a dual-address command comprising a source address and a destination address; generating a first content addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing, to the memory device, the read command associated with the first CAM entry.
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公开(公告)号：US11461030B2
公开(公告)日：2022-10-04
申请号：US16916926
申请日：2020-06-30
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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公开(公告)号：US11907563B2
公开(公告)日：2024-02-20
申请号：US17940751
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
CPC classification number: G06F3/0647 , G06F1/04 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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Patent Agency Ranking
公开(公告)号：US11861225B2
公开(公告)日：2024-01-02
申请号：US17464029
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Jiangli Zhu , Chih-Kuo Kao , Fangfang Zhu
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/0679 , G06F12/0238
Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising generating a super management unit (SMU) memory access command; splitting the SMU memory access command into a plurality of management unit (MU) memory access commands; indexing, in an index data structure, each MU memory access command of the plurality of MU memory access commands; issuing, to the memory device, a sequence of MU memory access commands from the plurality of MU memory access commands; receiving an indication that a MU memory access command from the sequence of MU memory access commands is completed; and responsive to determining that the completed MU memory access command satisfies a criterion, issuing an available MU memory access command based on an index value of the available MU memory access command.
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公开(公告)号：US20230066863A1
公开(公告)日：2023-03-02
申请号：US17459846
申请日：2021-08-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Juane Li , Fangfang Zhu , Seungjune Jeon , Yueh-Hung Chen
Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.
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公开(公告)号：US11860732B2
公开(公告)日：2024-01-02
申请号：US17459846
申请日：2021-08-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Juane Li , Fangfang Zhu , Seungjune Jeon , Yueh-Hung Chen
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/3037 , G06F12/0238 , G06F2212/7201
Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.
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公开(公告)号：US11823772B2
公开(公告)日：2023-11-21
申请号：US18105337
申请日：2023-02-03
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Chih-Kuo Kao , Yueh-Hung Chen , Jiangli Zhu
Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising receiving an indication that a first memory access operation performed in response to a first memory access command is complete, wherein the first memory access operation is associated with a first CAM entry comprising an identifier of a second CAM entry; identifying the second CAM entry using the indicator, wherein the second CAM entry references a second memory access command; and issuing, to the memory device, the second memory access command.
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公开(公告)号：US20210019071A1
公开(公告)日：2021-01-21
申请号：US16916926
申请日：2020-06-30
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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