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公开(公告)号：US12045512B2
公开(公告)日：2024-07-23
申请号：US18086580
申请日：2022-12-21
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhenming Zhou , Zhenlei Shen , Chih-Kuo Kao
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C7/1066 , G11C2207/2254
Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.
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公开(公告)号：US20240078048A1
公开(公告)日：2024-03-07
申请号：US18506505
申请日：2023-11-10
Applicant: Micron Technology, Inc.
Inventor： Juane Li , Fangfang Zhu , Jason Duong , Chih-Kuo Kao , Jiangli Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.
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公开(公告)号：US11747994B2
公开(公告)日：2023-09-05
申请号：US17462335
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Chih-Kuo Kao , Yi-Min Lin
CPC classification number: G06F3/0619 , G06F1/30 , G06F3/0632 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/3037
Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
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公开(公告)号：US11726815B2
公开(公告)日：2023-08-15
申请号：US16913751
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Jason Duong , Chih-Kuo Kao , Jiangli Zhu , Ying Yu Tai , Wei Wang
CPC classification number: G06F9/4881 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0683 , G06F9/3855
Abstract: Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.
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公开(公告)号：US11615826B1
公开(公告)日：2023-03-28
申请号：US17468044
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Chih-Kuo Kao , Yueh-Hung Chen , Jiangli Zhu
Abstract: A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device perform operations comprising: responsive to receiving a memory access command, determining that the memory access command is a dual-address command comprising a source address and a destination address; generating a first content addressable memory (CAM) entry associated with a read command of the dual-address command, wherein the first CAM entry references the source address; generating a second CAM entry associated with a write command of the dual-address command, wherein the second CAM entry references the destination address; inserting the first CAM entry and the second CAM entry into a CAM; and issuing, to the memory device, the read command associated with the first CAM entry.
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Patent Agency Ranking
公开(公告)号：US20230070078A1
公开(公告)日：2023-03-09
申请号：US17940751
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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公开(公告)号：US20240126480A1
公开(公告)日：2024-04-18
申请号：US18531329
申请日：2023-12-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jason Duong , Fangfang Zhu , Jiangli Zhu , Juane Li , Chih-Kuo Kao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.
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公开(公告)号：US11907563B2
公开(公告)日：2024-02-20
申请号：US17940751
申请日：2022-09-08
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Chih-Kuo Kao , Ying Yu Tai , Jiangli Zhu
CPC classification number: G06F3/0647 , G06F1/04 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.
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公开(公告)号：US11893280B2
公开(公告)日：2024-02-06
申请号：US17459343
申请日：2021-08-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jason Duong , Fangfang Zhu , Jiangli Zhu , Juane Li , Chih-Kuo Kao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.
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公开(公告)号：US11861225B2
公开(公告)日：2024-01-02
申请号：US17464029
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Yueh-Hung Chen , Jiangli Zhu , Chih-Kuo Kao , Fangfang Zhu
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/0679 , G06F12/0238
Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising generating a super management unit (SMU) memory access command; splitting the SMU memory access command into a plurality of management unit (MU) memory access commands; indexing, in an index data structure, each MU memory access command of the plurality of MU memory access commands; issuing, to the memory device, a sequence of MU memory access commands from the plurality of MU memory access commands; receiving an indication that a MU memory access command from the sequence of MU memory access commands is completed; and responsive to determining that the completed MU memory access command satisfies a criterion, issuing an available MU memory access command based on an index value of the available MU memory access command.
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