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公开(公告)号：US12111769B2
公开(公告)日：2024-10-08
申请号：US17630453
申请日：2021-03-16
IPC分类号： G06F12/0873
CPC分类号： G06F12/0873
摘要： Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
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公开(公告)号：US11989133B2
公开(公告)日：2024-05-21
申请号：US17637429
申请日：2021-03-16
IPC分类号： G06F12/10
CPC分类号： G06F12/10
摘要： Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).
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公开(公告)号：US20230359563A1
公开(公告)日：2023-11-09
申请号：US17630453
申请日：2021-03-16
IPC分类号： G06F12/0873
CPC分类号： G06F12/0873
摘要： Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
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公开(公告)号：US20230350808A1
公开(公告)日：2023-11-02
申请号：US17637429
申请日：2021-03-16
IPC分类号： G06F12/10
CPC分类号： G06F12/10
摘要： Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).
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公开(公告)号：US20230359551A1
公开(公告)日：2023-11-09
申请号：US17633523
申请日：2021-03-19
发明人： Xu Zhang , Jonathan S. Parry , Zhen Gu
IPC分类号： G06F12/0882 , G06F12/02 , G06F13/16
CPC分类号： G06F12/0246 , G06F12/0882 , G06F13/1668
摘要： Methods, systems, and devices for techniques for a fragment cursor are described. A memory system may receive one or more write commands, each write command corresponding to a data fragment. The memory device may store the data fragments to a cursor (e.g., a fragment cursor) in a cache upon receiving the write commands, the cursor configured to store data fragments with a size less than a fragment size threshold (e.g., a page). The memory system may detect a memory management operation (e.g., power down, cache synchronization, data relocation, etc.) and write the cached data fragments to a block of memory cells of a memory device using the cursor. In some examples, the cursor may have a different associated mapping unit than other cursors of the memory system.
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公开(公告)号：US20240193095A1
公开(公告)日：2024-06-13
申请号：US17758335
申请日：2022-03-17
发明人： Liping Xu , Zhen Gu , Qingyuan Wang
IPC分类号： G06F12/1009 , G06F12/1045
CPC分类号： G06F12/1009 , G06F12/1054 , G06F2212/7201
摘要： Methods, systems, and devices for a sorted change log for physical page table compression are described. A mapping between a logical address and a physical address may be stored in a change log buffer. The mapping may be stored at a location of the change log buffer based on the logical address of the mapping relative to logical addresses of other mappings stored in the change log buffer. Based on storing mappings in the change log buffer based on logical addresses of the mappings, a set of mappings in the change log may include a set of sequentially-indexed logical addresses. A compressed entry for a logical-to-physical table may be generated based on the set of mappings.
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公开(公告)号：US20230359365A1
公开(公告)日：2023-11-09
申请号：US17630113
申请日：2021-03-16
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/0634 , G06F3/0679 , G06F3/0659
摘要： Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.
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