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公开(公告)号：US10007235B2
公开(公告)日：2018-06-26
申请号：US15711012
申请日：2017-09-21
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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公开(公告)号：US20180088535A1
公开(公告)日：2018-03-29
申请号：US15711012
申请日：2017-09-21
IPC分类号： G04F10/00
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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