Lightweight transport protocol
    1.
    发明授权

    公开(公告)号:US10455061B2

    公开(公告)日:2019-10-22

    申请号:US15849609

    申请日:2017-12-20

    Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

    In-line network accelerator
    3.
    发明授权

    公开(公告)号:US10129153B2

    公开(公告)日:2018-11-13

    申请号:US15595925

    申请日:2017-05-15

    Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

    Processing Encoding Format to Interpret Information Regarding a Group of Instructions
    4.
    发明申请
    Processing Encoding Format to Interpret Information Regarding a Group of Instructions 审中-公开
    处理编码格式以解释有关一组说明的信息

    公开(公告)号:US20160378494A1

    公开(公告)日:2016-12-29

    申请号:US14752727

    申请日:2015-06-26

    CPC classification number: G06F9/3802 G06F9/3814 G06F9/3853

    Abstract: A method including fetching information regarding a group of instructions, where the group of instructions is configured to execute atomically by a processor, including an encoding format for the information regarding the group of instructions, is provided. The method further includes processing the encoding format to interpret the information regarding the group of instructions.

    Abstract translation: 提供了一种方法,其包括提取关于一组指令的信息,其中指令组被配置为由处理器原子地执行,包括用于关于指令组的信息的编码格式。 该方法还包括处理编码格式以解释关于指令组的信息。

    Decoding Information About a Group of Instructions Including a Size of the Group of Instructions
    5.
    发明申请
    Decoding Information About a Group of Instructions Including a Size of the Group of Instructions 审中-公开
    解码包含指令组大小的一组指令信息

    公开(公告)号:US20160378492A1

    公开(公告)日:2016-12-29

    申请号:US14752682

    申请日:2015-06-26

    Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor is provided. The method further includes decoding at least one of a first instruction or a second instruction, where: (1) decoding the first instruction results in a processing of information about a group of instructions, including information about a size of the group of instructions, and (2) decoding the second instruction results in a processing of at least one of: (a) a reference to a memory location having the information about the group of instructions, including information about the size of the group of instructions or (b) a processor status word having information about the group of instructions, including information about the size of the group of instructions.

    Abstract translation: 提供了一种方法,其包括获取一组指令,其中指令组被配置为由处理器原子地执行。 该方法还包括解码第一指令或第二指令中的至少一个,其中:(1)解码第一指令导致关于指令组的信息的处理,包括关于指令组的大小的信息,以及 (2)对第二指令进行解码得到以下至少之一的处理:(a)对具有关于指令组的信息的存储器位置的引用,包括关于指令组的大小的信息,或(b) 处理器状态字具有关于指令组的信息,包括关于指令组的大小的信息。

    Lightweight transport protocol
    6.
    发明授权

    公开(公告)号:US09888095B2

    公开(公告)日:2018-02-06

    申请号:US14752713

    申请日:2015-06-26

    CPC classification number: H04L69/165 H04L12/4633 H04L49/25 H04L49/30

    Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

    Locking Operand Values for Groups of Instructions Executed Atomically
    7.
    发明申请
    Locking Operand Values for Groups of Instructions Executed Atomically 审中-公开
    原子上执行的指令组的锁定操作数值

    公开(公告)号:US20160378495A1

    公开(公告)日:2016-12-29

    申请号:US14752792

    申请日:2015-06-26

    Inventor: Doug Burger

    CPC classification number: G06F9/3802 G06F9/38 G06F9/3814

    Abstract: A method including fetching a group of instructions, including a group header for the group of instructions, where the group of instructions is configured to execute by a processor, and where the group header includes a field including locking information for at least one operand is provided. The method further includes storing a value of the at least one operand in at least one operand buffer of the processor and based on the locking information, locking a value of the at least one operand in the at least one operand of the buffer such that the at least one operand is not cleared from the at least one operand buffer of the processor in response to completing the execution of the group of instructions.

    Abstract translation: 一种方法,包括获取一组指令,包括指令组的组头,其中指令组被配置为由处理器执行,并且其中组头包括包括至少一个操作数的锁定信息的字段 。 所述方法还包括将所述至少一个操作数的值存储在所述处理器的至少一个操作数缓冲器中,并且基于所述锁定信息,将所述至少一个操作数的值锁定在所述缓冲器的所述至少一个操作数中, 响应于完成指令组的执行,至少一个操作数不从处理器的至少一个操作数缓冲器中清除。

    Decoding information about a group of instructions including a size of the group of instructions

    公开(公告)号:US10409599B2

    公开(公告)日:2019-09-10

    申请号:US14752682

    申请日:2015-06-26

    Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor is provided. The method further includes decoding at least one of a first instruction or a second instruction, where: (1) decoding the first instruction results in a processing of information about a group of instructions, including information about a size of the group of instructions, and (2) decoding the second instruction results in a processing of at least one of: (a) a reference to a memory location having the information about the group of instructions, including information about the size of the group of instructions or (b) a processor status word having information about the group of instructions, including information about the size of the group of instructions.

    Locking operand values for groups of instructions executed atomically

    公开(公告)号:US10191747B2

    公开(公告)日:2019-01-29

    申请号:US14752792

    申请日:2015-06-26

    Inventor: Doug Burger

    Abstract: A method including fetching a group of instructions, including a group header for the group of instructions, where the group of instructions is configured to execute by a processor, and where the group header includes a field including locking information for at least one operand is provided. The method further includes storing a value of the at least one operand in at least one operand buffer of the processor and based on the locking information, locking a value of the at least one operand in the at least one operand of the buffer such that the at least one operand is not cleared from the at least one operand buffer of the processor in response to completing the execution of the group of instructions.

    IN-LINE NETWORK ACCELERATOR
    10.
    发明申请

    公开(公告)号:US20170250914A1

    公开(公告)日:2017-08-31

    申请号:US15595925

    申请日:2017-05-15

    Abstract: A smart NIC (Network Interface Card) is provided with features to enable the smart NIC to operate as an in-line NIC between a host's NIC and a network. The smart NIC provides pass-through transmission of network flows for the host. Packets sent to and from the host pass through the smart NIC. As a pass-through point, the smart NIC is able to accelerate the performance of the pass-through network flows by analyzing packets, inserting packets, dropping packets, inserting or recognizing congestion information, and so forth. In addition, the smart NIC provides a lightweight transport protocol (LTP) module that enables it to establish connections with other smart NICs. The LTP connections allow the smart NICs to exchange data without passing network traffic through their respective hosts.

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