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    Instruction for shifting bits left with pulling ones into less significant bits
    1.
    发明授权
    Instruction for shifting bits left with pulling ones into less significant bits 有权
    用于将位移位到较低有效位的指令

    公开(公告)号：US09122475B2

    公开(公告)日：2015-09-01

    申请号：US13630131

    申请日：2012-09-28

    申请人： Mikhail Plotnikov ,  Igor Ermolaev ,  Andrey Naraikin ,  Robert Valentine

    发明人： Mikhail Plotnikov ,  Igor Ermolaev ,  Andrey Naraikin ,  Robert Valentine

    IPC分类号： G06F9/30 ,  G06F15/80

    CPC分类号： G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/325

    摘要： A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.

    摘要翻译： 掩模生成指令由处理器执行以提高数据元素阵列上的向量操作的效率。 处理器包括向量寄存器，其中一个存储阵列的数据元素。 处理器还包括执行电路，用于接收指定至少第一操作数和第二操作数的掩码生成指令。 响应于掩模生成指令，执行电路是将第一操作数的位向左移动在第二操作数中定义的次数，并且每次将最高有效位 第一个操作数从左边移出来产生一个结果。 结果中的每个位对应于数组的数据元素之一。

    INSTRUCTION FOR SHIFTING BITS LEFT WITH PULLING ONES INTO LESS SIGNIFICANT BITS
    2.
    发明申请
    INSTRUCTION FOR SHIFTING BITS LEFT WITH PULLING ONES INTO LESS SIGNIFICANT BITS 有权
    用于将位移的位置指示，将其移动到较小的重要位置

    公开(公告)号：US20140095830A1

    公开(公告)日：2014-04-03

    申请号：US13630131

    申请日：2012-09-28

    申请人： Mikhail Plotnikov ,  Igor Ermolaev ,  Andrey Naraikin ,  Robert Valentine

    发明人： Mikhail Plotnikov ,  Igor Ermolaev ,  Andrey Naraikin ,  Robert Valentine

    IPC分类号： G06F9/315

    CPC分类号： G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/325

    摘要： A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.

    摘要翻译： 掩模生成指令由处理器执行以提高数据元素阵列上的向量操作的效率。 处理器包括向量寄存器，其中一个存储阵列的数据元素。 处理器还包括执行电路，用于接收指定至少第一操作数和第二操作数的掩码生成指令。 响应于掩模生成指令，执行电路是将第一操作数的位向左移动在第二操作数中定义的次数，并且每次将最高有效位 第一个操作数从左边移出来产生一个结果。 结果中的每个位对应于数组的数据元素之一。

    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE PERMUTE CONTROLS WITH LEADING ZERO COUNT FUNCTIONALITY
    4.
    发明申请
    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE PERMUTE CONTROLS WITH LEADING ZERO COUNT FUNCTIONALITY 有权
    方法，设备，说明和逻辑提供带有领先零点功能的PTE控制

    公开(公告)号：US20140189309A1

    公开(公告)日：2014-07-03

    申请号：US13731008

    申请日：2012-12-29

    申请人： Christopher J. Hughes ,  Mikhail Plotnikov ,  Andrey Naraikin ,  Robert Valentine

    发明人： Christopher J. Hughes ,  Mikhail Plotnikov ,  Andrey Naraikin ,  Robert Valentine

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3834

    摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

    摘要翻译： 说明和逻辑提供带有零计数功能的SIMD置换控制。 一些实施例包括具有多个数据字段的寄存器的处理器，每个数据字段用于存储第二多个位。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储对于相应数据字段设置为零的最重要连续位数的计数。 响应于对向量前导零计数指令进行解码，执行单元对寄存器中的每个数据字段计数设置为零的最高有效连续位的数目，并将计数存储在第一目的地寄存器的相应数据字段中。 向量前导零计数指令可用于生成与该组置换控制一起使用的置换控制和完成掩码，以解决采集修改散射SIMD操作中的依赖关系。