-
1.发明申请Vector instructions to enable efficient synchronization and parallel reduction operations 有权用于实现高效同步和并行还原操作的矢量指令公开(公告)号：US20090249026A1
公开(公告)日：2009-10-01
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能 响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。 描述和要求保护其他实施例。
-
2.发明授权公开(公告)号：US09513905B2
公开(公告)日：2016-12-06
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
-
公开(公告)号：US08688957B2
公开(公告)日：2014-04-01
申请号：US12974157
申请日：2010-12-21
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译： 将系统和方法配置为在将标量过程转换为并行进程（“SIMDifying”）时检测冲突。 可以针对无序单索引，有序单索引和/或有序索引对检测冲突。 读写依赖关系可能会进一步检测到冲突。 冲突检测被配置为识别可能不并行完成的迭代序列中的操作（即迭代）。
-
公开(公告)号：US20120159130A1
公开(公告)日：2012-06-21
申请号：US12974157
申请日：2010-12-21
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译： 将系统和方法配置为在将标量过程转换为并行进程（“SIMDifying”）时检测冲突。 可以针对无序单索引，有序单索引和/或有序索引对检测冲突。 读写依赖关系可能会进一步检测到冲突。 冲突检测被配置为识别可能不并行完成的迭代序列中的操作（即迭代）。
-
公开(公告)号：US08230172B2
公开(公告)日：2012-07-24
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
-
公开(公告)号：US08478941B2
公开(公告)日：2013-07-02
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
-
公开(公告)号：US20120290799A1
公开(公告)日：2012-11-15
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
-
公开(公告)号：US20110138122A1
公开(公告)日：2011-06-09
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译： 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。
-
9.发明申请公开(公告)号：US20140149718A1
公开(公告)日：2014-05-29
申请号：US13687918
申请日：2012-11-28
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/60 , G06F2212/621 , Y02D10/13
摘要： Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.
摘要翻译： 说明和逻辑提供推送缓冲区复制和存储功能。 一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。 响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据 当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。
-
公开(公告)号：US08667221B2
公开(公告)日：2014-03-04
申请号：US12099502
申请日：2008-04-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/128
摘要： An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement.
摘要翻译： 提出了一种在存储器中检测流数据的装置。 在一个实施例中，装置对高速缓存行使用重用位和S位状态，其中S位状态指示高速缓存行中的数据是潜在的流数据。 为了提高高速缓存的效率，可以采用不同的措施来使流数据成为替换期间的下一个受害者。
-
-
-
-
-
-
-
-
-
搜索结果
77 条记录 (耗时 0.038 秒)