公开(公告)号：US20070176235A1

公开(公告)日：2007-08-02

申请号：US11627167

申请日：2007-01-25

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

摘要翻译： 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。

公开(公告)号：US20060180861A1

公开(公告)日：2006-08-17

申请号：US11341444

申请日：2006-01-30

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

摘要翻译： 在半导体器件中，在由SOI衬底构成的SOI衬底的顶部上设置栅电极，杂质扩散区域，体电位固定区域，第一绝缘体和虚设栅电极，所述SOI衬底由下面的硅衬底，埋入绝缘体和 半导体层。 杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。 体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。 至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。 虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

公开(公告)号：US20050037524A1

公开(公告)日：2005-02-17

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

公开(公告)号：US08350331B2

公开(公告)日：2013-01-08

申请号：US11627167

申请日：2007-01-25

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

摘要翻译： 在半导体器件中，在相同的SOI衬底（硅支撑衬底，掩埋氧化物膜和硅层）上形成具有不同体膜厚度的体积薄膜晶体管和体薄膜晶体管。 体膜形成为比较厚的体膜厚晶体管，其具有凹陷结构，其中源/漏区的表面的水平低于体区的表面的水平，因此， 源极/漏极区域中的SOI膜形成为与体薄膜晶体管中的SOI膜一样薄。 另一方面，在体薄膜晶体管中，整个SOI膜形成为具有较薄的膜厚。 此外，源极/漏极区域形成为穿透硅层。

公开(公告)号：US07511342B2

公开(公告)日：2009-03-31

申请号：US11341444

申请日：2006-01-30

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L31/0392

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

摘要翻译： 在半导体器件中，在由SOI衬底，底层硅衬底，埋入绝缘体和 半导体层。 杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。 体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。 至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。 虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

公开(公告)号：US20060249756A1

公开(公告)日：2006-11-09

申请号：US11481799

申请日：2006-07-07

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L29/768

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.

摘要翻译： 半导体器件包括多个不同功能的电路部分，每个电路部分通过在通过顺序地堆叠半导体衬底，埋入绝缘膜和半导体层而获得的SOI衬底上包括MOS晶体管构成。 该半导体器件包括第一和第二部分。 第一电路部分通过被设置在半导体层的上部上的第一绝缘膜和穿过半导体层的第二绝缘膜包围而被隔离，以到达掩埋绝缘膜。

公开(公告)号：US07144764B2

公开(公告)日：2006-12-05

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/762

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3） 。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。

公开(公告)号：US20090127623A1

公开(公告)日：2009-05-21

申请号：US12354914

申请日：2009-01-16

申请人： Mikio TSUJIUCHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

发明人： Mikio TSUJIUCHI ,  Toshiaki Iwamatsu ,  Shigeto Maegawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

摘要翻译： 在半导体器件中，在由SOI衬底，底层硅衬底，埋入绝缘体和 半导体层。 杂质扩散区域是通过在栅电极周围的半导体层中注入第一导电类型的杂质形成的区域。 体电位固定区域是沿着栅电极的长度的延长线的方向设置的区域，并且注入第二导电类型的杂质。 至少在体电位固定区域和栅电极之间的部分形成第一绝缘体。 虚设栅电极设置在体电位固定区与栅电极之间的第一绝缘体上。

公开(公告)号：US06841400B2

公开(公告)日：2005-01-11

申请号：US10216363

申请日：2002-08-12

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S3）。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化氮化物膜22作为蚀刻掩模形成沟槽TR2（S4）。

公开(公告)号：US20050184342A1

公开(公告)日：2005-08-25

申请号：US11108843

申请日：2005-04-19

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L21/762 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/336 ,  H01L21/00 ,  H01L21/331 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。