公开(公告)号：US08743928B2

公开(公告)日：2014-06-03

申请号：US13547688

申请日：2012-07-12

申请人： Min-Chung Chou ,  Da-Rong Huang

发明人： Min-Chung Chou ,  Da-Rong Huang

IPC分类号： H04B1/00 ,  H04B3/46 ,  H04J11/00

CPC分类号： H04L25/03044 ,  H04L2025/03687

摘要： An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

摘要翻译： 公开了一种自适应均衡器及其操作方法。 自适应均衡器是基于过采样的。 自适应均衡器包括搜索模块，补偿模块和操作模块。 搜索模块根据监视器的第一监视结果，将均衡器设置从较低补偿搜索到较高补偿以获得第一均衡器设置值，然后将均衡器设置从较高补偿搜索到较低补偿，以获得第二均衡器设置 值根据监视器的第二个监视结果。 操作模块对第一均衡器设置值和第二均衡器设置值执行操作以获得优化的均衡器设置值。

公开(公告)号：US20130022098A1

公开(公告)日：2013-01-24

申请号：US13547688

申请日：2012-07-12

申请人： Min-Chung Chou ,  Da-Rong Huang

发明人： Min-Chung Chou ,  Da-Rong Huang

IPC分类号： H04L27/01

CPC分类号： H04L25/03044 ,  H04L2025/03687

摘要： An adaptive equalizer and operating method thereof are disclosed. The adaptive equalizer is oversampling-based. The adaptive equalizer includes a searching module, a compensation module, and an operating module. The searching module searches the equalizer setting from a lower compensation to a higher compensation to obtain a first equalizer setup value according a first monitored result of a monitor and then searches the equalizer setting from a higher compensation to a lower compensation to obtain a second equalizer setup value according to a second monitored result of the monitor. The operating module performs an operation on the first equalizer setup value and the second equalizer setup value to obtain an optimized equalizer setup value.

摘要翻译： 公开了一种自适应均衡器及其操作方法。 自适应均衡器是基于过采样的。 自适应均衡器包括搜索模块，补偿模块和操作模块。 搜索模块根据监视器的第一监视结果，将均衡器设置从较低补偿搜索到较高补偿以获得第一均衡器设置值，然后将均衡器设置从较高补偿搜索到较低补偿，以获得第二均衡器设置 值根据监视器的第二个监视结果。 操作模块对第一均衡器设置值和第二均衡器设置值执行操作以获得优化的均衡器设置值。

公开(公告)号：US20110043259A1

公开(公告)日：2011-02-24

申请号：US12917894

申请日：2010-11-02

申请人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

发明人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

IPC分类号： H03K3/00

CPC分类号： H03K19/018528 ,  H04L25/0272 ,  H04L25/028

摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

摘要翻译： 提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源 并且第一至第四开关装置用作电流转向电路。 在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号 来自前驱动器的信号。 在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

公开(公告)号：US07840194B2

公开(公告)日：2010-11-23

申请号：US11546919

申请日：2006-10-13

申请人： Yu-Hsin Wu ,  Min-Chung Chou ,  Hung-Chih Lin

发明人： Yu-Hsin Wu ,  Min-Chung Chou ,  Hung-Chih Lin

IPC分类号： H04B1/02

CPC分类号： G06F13/4072

摘要： A transmitter circuit, a receiver circuit and an interface switching module for SATA or SAS interface are provided. The invention uses transistors as elements with different impedance and also provides impedance modulating method in coordination with the exterior circuit and the layout design so as to develop an auto-switching mechanism between SATA and SAS interfaces, thereby integrating two transmission interfaces in a single system.

摘要翻译： 提供发射机电路，接收机电路和用于SATA或SAS接口的接口切换模块。 本发明使用晶体管作为具有不同阻抗的元件，并且还提供与外部电路和布局设计协调的阻抗调制方法，以便在SATA和SAS接口之间开发自动切换机制，从而在单个系统中集成两个传输接口。

公开(公告)号：US20090146726A1

公开(公告)日：2009-06-11

申请号：US11951331

申请日：2007-12-06

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： H01L35/00

CPC分类号： H03K5/133 ,  H03K2005/00143

摘要： A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.

摘要翻译： 延迟电路具有：具有电阻元件的反相接收器，反相接收器具有用于接收输入信号的输入节点和耦合到电阻元件的输出节点; 电容元件，耦合到反相接收器的输出节点和电阻元件; 第一晶体管，在较高温度下具有较低的导通电压; 第二晶体管，用于在第一晶体管的端子上产生轨到轨信号; 以及输出反相器，其具有耦合到第一晶体管的输入节点和用于输出延迟电路的输出信号的输出节点。 此外，第三晶体管用于增强延迟电路的输出信号的拉低。

公开(公告)号：US07358780B2

公开(公告)日：2008-04-15

申请号：US11287396

申请日：2005-11-28

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H04L25/0276 ,  H03F3/45179 ,  H03F3/45632 ,  H04L25/028

摘要： A LVDS (Low Voltage Differential Signal) driver with a high PSRR (Power Supply Rejection Ration) includes a first current source for providing a working current, a switch unit for receiving the working current and determining the current directions of an output current at first and second signal nodes according to first and second input signals, a second current source connected between the switch unit and a low working power voltage, a common mode feedback unit for generating a common mode control signal according to voltages on the first and second signal nodes of the switch unit, a common mode resistance unit connected in parallel with the second current source and having a resistance value controlled by the common mode control signal, and a compensation unit connected in parallel with the second current source for compensating the current variation of the first current source caused by power noise.

摘要翻译： 具有高PSRR（电源抑制比）的LVDS（低电压差分信号）驱动器包括用于提供工作电流的第一电流源，用于接收工作电流的开关单元，以及首先确定输出电流的电流方向， 根据第一和第二输入信号的第二信号节点，连接在开关单元和低工作电源电压之间的第二电流源，用于根据第一和第二信号节点上的电压产生共模控制信号的共模反馈单元 开关单元，与第二电流源并联并具有由共模控制信号控制的电阻值的共模电阻单元，以及与第二电流源并联连接的补偿单元，用于补偿第一电流源的电流变化 电源由电源噪声引起。

公开(公告)号：US07106644B2

公开(公告)日：2006-09-12

申请号：US10724657

申请日：2003-12-01

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C29/00

CPC分类号： G11C29/12005 ,  G11C11/401 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1202

摘要： A memory device and a method for burn in test are characterized by a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

摘要翻译： 一种存储器件和一种用于烧录测试的方法的特征在于多个子阵列字线漏电限制单元和多个单字线漏电限制单元。 它们用于将每个字线中的电流限制为预定的字线电流值。 在老化测试模式下，字线驱动器的输出保持在高阻抗状态。 位线应力电压通过正常读写路径施加到存储单元行。 还提供了用于产生基本上稳定的电压的电压发生器。 在老化测试模式下，偶数字线和奇数字线被分开分组，并且字线应力电压交替地施加到偶数字线和奇数字线。

公开(公告)号：US07099224B2

公开(公告)日：2006-08-29

申请号：US11250073

申请日：2005-10-13

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C5/14

CPC分类号： G11C29/12005 ,  G11C11/401 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1202

摘要： A memory device and a method for burn-in test. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

摘要翻译： 一种记忆装置和一种老化测试方法。 存储器件具有多个子阵列字线泄漏限制单元和多个单个字线泄漏电流限制单元。 它们用于将每个字线中的电流限制为预定的字线电流值。 在老化测试模式下，字线驱动器的输出保持在高阻抗状态。 位线应力电压通过正常读写路径施加到存储单元行。 还提供了用于产生基本上稳定的电压的电压发生器。 在老化测试模式下，偶数字线和奇数字线被分开分组，并且字线应力电压交替地施加到偶数字线和奇数字线。

公开(公告)号：US06262919B1

公开(公告)日：2001-07-17

申请号：US09544248

申请日：2000-04-05

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C700

CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

摘要： A laser signature circuit in a memory device comprises input pins for input signal into the memory device; internal circuits of the memory device connected to the input pins; a laser signature circuit connected between the internal circuits, wherein the laser signature circuit comprises a fuse to identify the memory device, the fuse is tested by input a signal into a first input pin of the input pins and the signal is measured on a second input pin of the input pins which is not necessary adjacent to the first input pin.

摘要翻译： 存储器件中的激光签名电路包括用于输入到存储器件中的信号的输入引脚; 存储器件的内部电路连接到输入引脚; 连接在内部电路之间的激光签名电路，其中激光签名电路包括用于识别存储器件的熔丝，通过将信号输入到输入引脚的第一输入引脚来测试熔丝，并且在第二输入端测量信号 不需要与第一输入引脚相邻的输入引脚的引脚。

公开(公告)号：US20130021862A1

公开(公告)日：2013-01-24

申请号：US13185515

申请日：2011-07-19

申请人： Min-Chung Chou

发明人： Min-Chung Chou

IPC分类号： G11C29/12

CPC分类号： G11C29/006 ,  G11C11/40 ,  G11C29/06

摘要： A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.

摘要翻译： 提供了动态随机存取存储器（DRAM）和用于测试DRAM的方法。 DRAM包括存储单元，与存储单元相关联的位线，本地缓冲器和位线读出放大器（BLSA）。 本地缓冲器接收作为电源的第一电源电压。 当数据信号被取消置位时，本地缓冲器向位线提供接地电压，并且当数据信号被断言时，该位线将第一电源电压提供给位线。 BLSA接收第二个电源电压作为电源。 当数据信号和晶片级老化测试信号都被断言时，BLSA向位线提供第二电源电压。 第二电源电压可能高于第一电源电压。 当DRAM处于晶片级老化测试模式时，晶片级老化测试信号被置位。