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1.发明申请Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line 失效选择性地激活由行地址启用的字线段和具有字线的部分激活命令的半导体存储器件的方法公开(公告)号：US20050068840A1
公开(公告)日：2005-03-31
申请号：US10943514
申请日：2004-09-17
申请人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
发明人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
IPC分类号： G11C11/407 , G11C8/02 , G11C8/08 , G11C11/401 , G11C11/4063
CPC分类号： G11C8/12
摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.
摘要翻译： 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。
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2.发明授权Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line 失效选择性地激活由行地址启用的字线段和具有字线的部分激活命令的半导体存储器件的方法公开(公告)号：US07187615B2
公开(公告)日：2007-03-06
申请号：US10943514
申请日：2004-09-17
申请人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
发明人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.
摘要翻译： 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。
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3.发明授权Signature circuit, semiconductor device having the same and method of reading signature information 有权签名电路，具有相同的半导体器件和读取签名信息的方法公开(公告)号：US07506234B2
公开(公告)日：2009-03-17
申请号：US11472850
申请日：2006-06-22
申请人： Yu-Lim Lee , Sung-Hoon Kim
发明人： Yu-Lim Lee , Sung-Hoon Kim
IPC分类号： G01R31/28
CPC分类号： H01L23/585 , G11C29/028 , G11C29/50008 , G11C2029/4402 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.
摘要翻译： 半导体芯片中的签名电路包括签名程序电路，其被配置为对签名信息进行编程，并响应于签名信息输出签名信号; 签名输出电路，被配置为在正常模式下操作期间阻止由所述签名程序电路输出的签名信号，并且被配置为在测试模式下操作期间传递所述签名信号; 以及焊盘驱动晶体管，其直接耦合到所述焊盘，被配置为响应于操作命令在正常模式下操作期间驱动焊盘，并且被配置为响应于在测试模式中的操作期间响应于由 签名输出电路。 签名电路通过用于调整阻抗的晶体管输出签名信息，以通过省略签名电路的附加逻辑电路来减小芯片尺寸。
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公开(公告)号：US07443756B2
公开(公告)日：2008-10-28
申请号：US11565821
申请日：2006-12-01
申请人： Yu-Lim Lee , Sung-Hoon Kim
发明人： Yu-Lim Lee , Sung-Hoon Kim
IPC分类号： G11C17/18
CPC分类号： G11C29/787
摘要： A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may be alternately arranged in an X-axis direction or a Y-axis direction of a wafer. Accordingly, a tester may repair defective rows or columns of the two banks without shifting from one axis.
摘要翻译： 布置冗余熔丝块阵列的方法可以减少存储器件的测试时间。 存储器件可以包括堆栈组结构，其中至少两个存储体共享行解码器或列解码器。 用于两组的冗余保险丝座阵列可以在晶片的X轴方向或Y轴方向上交替布置。 因此，测试者可以修复两个组的有缺陷的行或列而不从一个轴移动。
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5.发明申请Signature circuit, semiconductor device having the same and method of reading signature information 有权签名电路，具有相同的半导体器件和读取签名信息的方法公开(公告)号：US20070030051A1
公开(公告)日：2007-02-08
申请号：US11472850
申请日：2006-06-22
申请人： Yu-Lim Lee , Sung-Hoon Kim
发明人： Yu-Lim Lee , Sung-Hoon Kim
IPC分类号： H01H37/76
CPC分类号： H01L23/585 , G11C29/028 , G11C29/50008 , G11C2029/4402 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.
摘要翻译： 半导体芯片中的签名电路包括签名程序电路，其被配置为对签名信息进行编程，并响应于签名信息输出签名信号; 签名输出电路，被配置为在正常模式下操作期间阻止由所述签名程序电路输出的签名信号，并且被配置为在测试模式下操作期间传递所述签名信号; 以及焊盘驱动晶体管，其直接耦合到所述焊盘，被配置为响应于操作命令在正常模式下操作期间驱动焊盘，并且被配置为响应于在测试模式中的操作期间响应于由 签名输出电路。 签名电路通过用于调整阻抗的晶体管输出签名信息，以通过省略签名电路的附加逻辑电路来减小芯片尺寸。
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