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1.发明申请公开(公告)号：US20130187686A1
公开(公告)日：2013-07-25
申请号：US13569568
申请日：2012-08-08
申请人： Min-Shueh YUAN , Chien-Hung CHEN , Shao-Yu LI
发明人： Min-Shueh YUAN , Chien-Hung CHEN , Shao-Yu LI
IPC分类号： H03B19/12 , H03K19/096
CPC分类号： H03K3/0375
摘要： In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes.
摘要翻译： 响应于第一级时钟信号，触发器电路的反相输出经由其非反相输入连接到触发器电路的第一中间节点，并且该反相输出端 触发器电路经由其反相输入连接到触发器电路的第二中间节点。 响应于时钟信号的第二电平，第一中间节点经由触发器电路的第三中间节点连接到非反相输出端，并且第二中间节点经由第四中间节点 触发器电路，到反相输出。 触发器电路的第一交叉耦合门装置耦合在第一和第二中间节点之间。 触发器电路的第二交叉耦合栅极布置耦合在第三和第四中间节点之间。
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公开(公告)号：US20130038366A1
公开(公告)日：2013-02-14
申请号：US13205722
申请日：2011-08-09
CPC分类号： G01R31/3016 , G01R31/31725 , G01R31/31726 , G01R31/31727 , G01R31/3187
摘要： A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.
摘要翻译： 用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路 周期到电流转换电路。 相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。
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公开(公告)号：US20140266114A1
公开(公告)日：2014-09-18
申请号：US14291426
申请日：2014-05-30
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： H02M3/158
摘要： A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
摘要翻译： 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。
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4.发明申请公开(公告)号：US20100253303A1
公开(公告)日：2010-10-07
申请号：US12750260
申请日：2010-03-30
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： G05F1/10
摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.
摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。
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公开(公告)号：US20130127433A1
公开(公告)日：2013-05-23
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： G05F1/44
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译： 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。
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公开(公告)号：US20130063181A1
公开(公告)日：2013-03-14
申请号：US13228508
申请日：2011-09-09
申请人： Mao-Hsuan CHOU , Min-Shueh YUAN , Chih-Hsien CHANG
发明人： Mao-Hsuan CHOU , Min-Shueh YUAN , Chih-Hsien CHANG
IPC分类号： H03D13/00
摘要： A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.
摘要翻译： 用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。 这些信号具有共同的频率并且相互偏移倍数的相位偏移。 检测到第一信号的边缘。 第一个信号是参考信号的多个相移版本之一。 边缘是从第一逻辑值到第二逻辑值的转换。 第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。 基于比较的结果选择性地提供第一信号的反转。
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