Content addressable memory design
    1.
    发明授权
    Content addressable memory design 有权
    内容可寻址内存设计

    公开(公告)号:US08395920B2

    公开(公告)日:2013-03-12

    申请号:US12788924

    申请日:2010-05-27

    IPC分类号: G11C15/00

    摘要: A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.

    摘要翻译: 静态CAM包括多个条目E,每个条目E包括多个CAM单元B和概要S.每个CAM单元B与存储单元M和比较器C相关联。通常,CAM接收到i个查找数据 线条。 当接收到数据时,存储器单元M提供CAM单元B中对应的比较器C的比较数据,以将比较的数据与接收到的数据进行比较。 如果所有比较的数据匹配所有接收到的数据行的条目,则该条目的命中。 但是,如果任何比较的数据与相应的数据行不匹配,那么该行有一个缺失,因此该条目的缺失。 根据应用程序,如果有一个或多个条目的命中,CAM将返回一个地址。

    Voltage regulator with high accuracy and high power supply rejection ratio
    2.
    发明授权
    Voltage regulator with high accuracy and high power supply rejection ratio 有权
    电压调节器具有高精度和高电源抑制比

    公开(公告)号:US08378654B2

    公开(公告)日:2013-02-19

    申请号:US12750260

    申请日:2010-03-30

    IPC分类号: G05F1/44

    CPC分类号: H02M3/158 G05F1/44 G05F1/56

    摘要: A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

    摘要翻译: 提供了具有高精度和电源抑制比(PSRR)的稳压电路。 在一个实施例中,具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压,以进一步提高高频PSRR。 在另一个实施例中,PMOS和NMOS晶体管的作用相反。

    Memory circuits, systems, and method of interleaving accesses thereof
    3.
    发明授权
    Memory circuits, systems, and method of interleaving accesses thereof 有权
    存储器电路,系统及其访问方法

    公开(公告)号:US08164974B2

    公开(公告)日:2012-04-24

    申请号:US12698423

    申请日:2010-02-02

    IPC分类号: G11C11/00

    CPC分类号: G11C7/1042 G11C8/04

    摘要: An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

    摘要翻译: 交错存储器电路包括具有第一存储单元的第一存储器组。 第一本地控制电路与第一存储体耦合。 第二存储器组包括第二存储器单元。 第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。 全局控制电路与第一和第二本地控制电路耦合。 交织接入包括具有第一周期和第二周期的时钟信号,用于分别访问第一存储器单元和第二存储单元,其中第二周期能够使第一本地控制电路触发第一 读取列选择信号RSSL用于访问第一个存储单元。

    MEMORY DEVICES HAVING BREAK CELLS
    4.
    发明申请
    MEMORY DEVICES HAVING BREAK CELLS 有权
    具有断裂细胞的记忆装置

    公开(公告)号:US20120051112A1

    公开(公告)日:2012-03-01

    申请号:US12870925

    申请日:2010-08-30

    IPC分类号: G11C5/02

    CPC分类号: G11C5/02 G11C11/417

    摘要: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.

    摘要翻译: 代表性的存储器件包括单元阵列,至少一个将单元阵列细分为位单元阵列的中断单元以及电耦合到位单元的一个或多个功率开关。 在一个实施例中,中断单元在至少两个位单元阵列之间分离第一电压和第二电压的连通性,使得位单元阵列可以使用功率开关选择性地耦合到第一电压或第二电压。 电源开关将单元阵列的每个分离的位单元阵列的连接控制为第一电压或第二电压。

    Content addressable memory
    5.
    发明授权
    Content addressable memory 有权
    内容可寻址内存

    公开(公告)号:US09280633B2

    公开(公告)日:2016-03-08

    申请号:US14279406

    申请日:2014-05-16

    摘要: A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.

    摘要翻译: 设计内容寻址存储器(CAM)的方法包括将CAM单元与汇总电路相关联。 汇总电路包括第一级逻辑门和第二级逻辑门。 第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。 逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。 选择第一级逻辑门或第二级逻辑门中的至少一个的逻辑门具有奇数个输入引脚,使得输入引脚和输出引脚共享布局子时隙。

    Electrical fuse programming time control scheme
    6.
    发明授权
    Electrical fuse programming time control scheme 有权
    电熔丝编程时间控制方案

    公开(公告)号:US08427857B2

    公开(公告)日:2013-04-23

    申请号:US12774851

    申请日:2010-05-06

    IPC分类号: G11C17/00

    CPC分类号: G11C17/16 G11C17/18

    摘要: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

    摘要翻译: 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极,以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

    SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION
    7.
    发明申请
    SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION 有权
    SRAM BITCELL数据保护控制用于泄漏优化

    公开(公告)号:US20120026805A1

    公开(公告)日:2012-02-02

    申请号:US12846129

    申请日:2010-07-29

    IPC分类号: G11C7/00 G11C5/14

    CPC分类号: G11C11/412 G11C5/147

    摘要: An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level.

    摘要翻译: 集成电路包括耦合到第一电压供应节点和第二电压供应节点的静态随机存取存储器(SRAM)阵列。 第一和第二电压供应节点提供跨SRAM阵列的保持电压。 限流器设置在SRAM阵列和第一电压供应节点之间,并且电压调节器与SRAM阵列和第一电压供应节点之间的限流器并联耦合。 电压调节器被配置为将SRAM阵列上的保持电压保持在预定水平以上。

    System and method for effectively implementing a high speed DRAM device
    8.
    发明授权
    System and method for effectively implementing a high speed DRAM device 失效
    有效实施高速DRAM器件的系统和方法

    公开(公告)号:US06798687B2

    公开(公告)日:2004-09-28

    申请号:US10320056

    申请日:2002-12-16

    IPC分类号: G11C700

    摘要: A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a wordline for enabling an accelerated-write operation in the memory cell, and a data storage node with a corresponding cell voltage. An accelerated-write circuit may then directly provide the storage data to an appropriate bitline in a pre-toggled state in response to one or more accelerated-write enable signals. The corresponding cell voltage may therefore begin a state-change transition towards the pre-toggled state immediately after the wordline is activated to successfully reach a full-state level before the wordline is deactivated during a high-speed memory cycle.

    摘要翻译: 用于有效实现高速DRAM设备的系统和方法可以包括每个具有用于传送存储数据的位线的存储器单元,用于在存储单元中启用加速写入操作的字线以及具有相应单元的数据存储节点 电压。 响应于一个或多个加速写入使能信号,加速写入电路然后可以以预切换状态直接将存储数据提供给适当的位线。 因此,在高速存储器周期中,在字线被禁用之前,相应的单元电压可能在字线被激活以成功地达到满状态电平之后立即开始朝向预切换状态的状态转变。

    METHOD OF OPERATING VOLTAGE REGULATOR
    9.
    发明申请
    METHOD OF OPERATING VOLTAGE REGULATOR 有权
    操作电压调节器的方法

    公开(公告)号:US20140266114A1

    公开(公告)日:2014-09-18

    申请号:US14291426

    申请日:2014-05-30

    IPC分类号: H02M3/158

    CPC分类号: H02M3/158 G05F1/44 G05F1/56

    摘要: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

    摘要翻译: 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点,第一功率节点,第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号,该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

    Method and apparatus for memory cell layout
    10.
    发明授权
    Method and apparatus for memory cell layout 有权
    用于存储单元布局的方法和装置

    公开(公告)号:US08450778B2

    公开(公告)日:2013-05-28

    申请号:US12862387

    申请日:2010-08-24

    IPC分类号: H01L27/11

    摘要: A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.

    摘要翻译: 半导体器件分别在阵列的第一和第二列中具有第一和第二互连结构。 第一和第二互连结构中的每一个具有参考电压节点和彼此耦合并分别形成在第一层,第二层,第三层和第四层上的第一,第二,第三和第四导体 在具有限定多个位单元的多个器件的衬底上。 每个互连结构的参考电压节点向对应于所述互连结构的位单元提供分别分离的参考电压。 在互连结构中的第一,第二,第三和第四导体中的任一个都不连接到另一个互连结构中的相应导体。 第二层在第一层之上,第三层位于第二层之上,第四层位于第三层之上。