公开(公告)号：US20100153636A1

公开(公告)日：2010-06-17

申请号：US12635828

申请日：2009-12-11

申请人： Ming Chuan HUANG ,  Chia Hao Lee ,  Han Liang Chou

发明人： Ming Chuan HUANG ,  Chia Hao Lee ,  Han Liang Chou

IPC分类号： G06F12/00

CPC分类号： G06F12/0607 ,  G06F13/1626

摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

摘要翻译： 用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。 系统存储器访问命令缓冲器存储多个系统存储器访问命令。 存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置 优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。 读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

公开(公告)号：US08250322B2

公开(公告)日：2012-08-21

申请号：US12635828

申请日：2009-12-11

申请人： Ming Chuan Huang ,  Chia Hao Lee ,  Han Liang Chou

发明人： Ming Chuan Huang ,  Chia Hao Lee ,  Han Liang Chou

IPC分类号： G06F13/18

CPC分类号： G06F12/0607 ,  G06F13/1626

摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

摘要翻译： 用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。 系统存储器访问命令缓冲器存储多个系统存储器访问命令。 存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置 优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。 读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

公开(公告)号：US20110019489A1

公开(公告)日：2011-01-27

申请号：US12656216

申请日：2010-01-21

申请人： Ming-Chuan Huang ,  Chien-Piao Lan ,  Chia Hao Lee

发明人： Ming-Chuan Huang ,  Chien-Piao Lan ,  Chia Hao Lee

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1093 ,  G11C8/18

摘要： An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

摘要翻译： 用于SDRAM接口的数据选通和定时变化检测的装置包括差分信号到单端信号转换器，第一相位延迟电路，数据锁存电路。 差分信号到单端信号转换器从SDRAM接口接收差分数据选通信号，并将该信号转换为单端数据选通信号。 第一相位延迟电路连接到差分信号到单端信号转换器，以延迟单端数据选通信号的相位，以产生延迟的数据选通信号。 数据锁存电路连接到相位延迟电路，根据延迟的单端数据选通信号，从SDRAM接口锁存同步数据。

公开(公告)号：US08208321B2

公开(公告)日：2012-06-26

申请号：US12656216

申请日：2010-01-21

申请人： Ming-Chuan Huang ,  Chien-Piao Lan ,  Chia Hao Lee

发明人： Ming-Chuan Huang ,  Chien-Piao Lan ,  Chia Hao Lee

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1093 ,  G11C8/18

摘要： An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

摘要翻译： 用于SDRAM接口的数据选通和定时变化检测的装置包括差分信号到单端信号转换器，第一相位延迟电路，数据锁存电路。 差分信号到单端信号转换器从SDRAM接口接收差分数据选通信号，并将该信号转换为单端数据选通信号。 第一相位延迟电路连接到差分信号到单端信号转换器，以延迟单端数据选通信号的相位，以产生延迟的数据选通信号。 数据锁存电路连接到相位延迟电路，根据延迟的单端数据选通信号，从SDRAM接口锁存同步数据。

公开(公告)号：US08466050B2

公开(公告)日：2013-06-18

申请号：US12830241

申请日：2010-07-02

申请人： Hanming Wu ,  Chia Hao Lee ,  John Chen

发明人： Hanming Wu ,  Chia Hao Lee ,  John Chen

IPC分类号： H01L21/425

CPC分类号： H01J37/3171 ,  H01J37/3007 ,  H01J2237/055 ,  H01J2237/0825 ,  H01L21/2236 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

摘要翻译： 一种在半导体衬底中形成轻掺杂漏极（LDD）区域的方法。 该方法包括产生所选物种的离子束并加速离子束，其中加速离子束包括第一加速部分和第二加速部分。 该方法还包括偏转加速离子束，其中第一和第二加速部分同时偏转到具有第一偏转角的第一路径轨迹和具有第二偏转角的第二路径轨迹。 在一个实施例中，第一和第二路径轨迹在与半导体晶片的表面区域垂直的相同方向上行进，并且第一偏转角度大于第二偏转角度。 在一个实施方案中，所选择的物质可​​以包括包含磷（P），砷（As）或锑（Sb）的n型离子。

公开(公告)号：US07721166B2

公开(公告)日：2010-05-18

申请号：US12057234

申请日：2008-03-27

申请人： Szu I Yeh ,  Hsin Jen Huang ,  Chien Cheng Lin ,  Chia Hao Lee ,  Chih Nan Yen ,  Fuja Shone

发明人： Szu I Yeh ,  Hsin Jen Huang ,  Chien Cheng Lin ,  Chia Hao Lee ,  Chih Nan Yen ,  Fuja Shone

IPC分类号： G11C29/00

CPC分类号： G11C29/72 ,  G11C2029/4402

摘要： A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

摘要翻译： 用于管理非易失性存储器中的缺陷块的方法基本上包括以下步骤：检测非易失性存储器中的缺陷块，将缺陷块的地址存储在非易失性存储器的表块中，并且设置非易失性存储器 如果非易失性存储器中的缺陷块的数量超过阈值并且在非易失性存储器中不存在空闲块，则存储器将是只读的。 在优选实施例中，在将非易失性存储器设置为只读之前，缺陷块中的空闲页面继续被编程。

公开(公告)号：US20110143512A1

公开(公告)日：2011-06-16

申请号：US12830241

申请日：2010-07-02

申请人： HANMING WU ,  Chia Hao Lee ,  John Chen

发明人： HANMING WU ,  Chia Hao Lee ,  John Chen

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01J1/50

CPC分类号： H01J37/3171 ,  H01J37/3007 ,  H01J2237/055 ,  H01J2237/0825 ,  H01L21/2236 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

摘要翻译： 一种在半导体衬底中形成轻掺杂漏极（LDD）区域的方法。 该方法包括产生所选物种的离子束并加速离子束，其中加速离子束包括第一加速部分和第二加速部分。 该方法还包括偏转加速离子束，其中第一和第二加速部分同时偏转到具有第一偏转角的第一路径轨迹和具有第二偏转角的第二路径轨迹。 在一个实施例中，第一和第二路径轨迹在与半导体晶片的表面区域垂直的相同方向上行进，并且第一偏转角度大于第二偏转角度。 在一个实施方案中，所选择的物质可​​以包括包含磷（P），砷（As）或锑（Sb）的n型离子。

公开(公告)号：US20090249140A1

公开(公告)日：2009-10-01

申请号：US12057234

申请日：2008-03-27

申请人： Szu I. Yeh ,  Hsin Jen Huang ,  Chien Cheng Lin ,  Chia Hao Lee ,  Chih Nan Yen ,  Fuja Shone

发明人： Szu I. Yeh ,  Hsin Jen Huang ,  Chien Cheng Lin ,  Chia Hao Lee ,  Chih Nan Yen ,  Fuja Shone

IPC分类号： G11C29/10 ,  G06F11/22

CPC分类号： G11C29/72 ,  G11C2029/4402

摘要： A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

摘要翻译： 用于管理非易失性存储器中的缺陷块的方法基本上包括以下步骤：检测非易失性存储器中的缺陷块，将缺陷块的地址存储在非易失性存储器的表块中，并且设置非易失性存储器 如果非易失性存储器中的缺陷块的数量超过阈值并且在非易失性存储器中不存在空闲块，则存储器将是只读的。 在优选实施例中，在将非易失性存储器设置为只读之前，缺陷块中的空闲页面继续被编程。

公开(公告)号：US20100003799A1

公开(公告)日：2010-01-07

申请号：US12258375

申请日：2008-10-24

申请人： Chia Hao Lee

发明人： Chia Hao Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/2236 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a MOS device with an ultra shallow lightly doped diffusion region. The method includes providing a semiconductor substrate including a surface region. The method provides a gate dielectric layer overlying the surface region and forms a gate structure overlying a portion of the gate dielectric layer. The method includes performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask. In a specific embodiment, the method includes performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask. The method includes performing a first thermal process to activate the P type impurity in the lightly doped drain region. The method includes forming side wall spacers overlying a portion of the gate structure and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region of the semiconductor substrate adjacent to the gate structure using the gate structure and the side wall spacer as a masking layer. The method then performs a second thermal process to activate the first impurity in the active source/drain regions.

摘要翻译： 一种用于形成具有超浅轻掺杂扩散区的MOS器件的方法。 该方法包括提供包括表面区域的半导体衬底。 该方法提供覆盖在表面区域上的栅介质层，并形成覆盖栅极电介质层的一部分的栅极结构。 该方法包括使用锗物质进行第一注入工艺，以使用栅极结构作为掩模在半导体衬底中的轻掺杂漏极区域内形成非晶区域。 在具体实施例中，该方法包括使用P型杂质和使用栅极结构作为掩模的碳物质在轻掺杂漏极区域中执行第二注入工艺。 该方法包括执行第一热处理以激活轻掺杂漏极区中的P型杂质。 该方法包括形成覆盖栅极结构的一部分的侧壁间隔物，并且使用第一杂质执行第三注入工艺，以使用栅极结构在邻近栅极结构的半导体衬底的表面区域附近形成有源源极/漏极区域 结构和侧壁间隔物作为掩蔽层。 该方法然后执行第二热处理以激活有源源极/漏极区域中的第一杂质。

公开(公告)号：US20090269865A1

公开(公告)日：2009-10-29

申请号：US12238689

申请日：2008-09-26

申请人： Chia Hao Lee

发明人： Chia Hao Lee

IPC分类号： H01L21/28 ,  H01L21/66

CPC分类号： H01L21/28035

摘要： A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.

摘要翻译： 一种用于制造MOS器件的方法。 该方法包括提供半导体衬底。 该方法形成覆盖半导体衬底的栅介质层和覆盖栅介电层的多晶硅栅极。 多晶硅栅极的特征在于厚度，宽度和多晶硅基底轮廓。 在一个具体实施例中，该方法执行TCAD仿真并且确定由于来自模型的多晶硅基础概况而导致的器件性能的响应。 该方法使用该模型来提供用于制造多晶硅栅极的工艺控制窗口。