公开(公告)号：US06747861B2

公开(公告)日：2004-06-08

申请号：US09987616

申请日：2001-11-15

Applicant: Ming-Dou Ker ,  Chien-Hui Chung ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Chien-Hui Chung ,  Hsin-Chin Jiang

IPC: H02H904

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge protection circuit that includes a rectifier, having an anode and a cathode, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion is coupled to the anode and the second n-type portion is coupled to the cathode, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier, and a voltage coupling circuit having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal is coupled to the anode of the rectifier, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistors, and the fourth terminal is coupled to the cathode.

Abstract translation: 一种静电放电保护电路，包括具有阳极和阴极的整流器，包括第一p型部分，与第一p型部分相邻的第一n型部分，与第一p型部分邻接的第二p型部分 n型部分和与第二p型部分邻接的第二n型部分，其中第一p型部分耦合到阳极，第二n型部分耦合到阴极，第一晶体管具有 第一端子，第二端子和栅极端子，其中第一端子耦合到整流器的第一n型部分，具有第一端子，第二端子和栅极端子的第二晶体管，其中第一端子是 耦合到第一晶体管的第二端子，并且第二端子耦合到整流器的第二n型部分，以及具有第一端子，第二端子，第三端子和第四端子的电压耦合电路， 其中 第一端子耦合到整流器的阳极，第二和第三端子分别耦合到第一和第二晶体管的栅极端子，并且第四端子耦合到阴极。

公开(公告)号：US08116049B2

公开(公告)日：2012-02-14

申请号：US12625449

申请日：2009-11-24

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang ,  Wen-Yi Chen

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang ,  Wen-Yi Chen

IPC: H02H3/22

CPC classification number: H02H9/046 ,  H02H1/0007

Abstract: The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

Abstract translation: 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。 晶体管与电容器耦合，检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此，形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。

公开(公告)号：US07394630B2

公开(公告)日：2008-07-01

申请号：US10268756

申请日：2002-10-11

Applicant: Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

IPC: H02H3/22

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

Abstract translation: 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。

公开(公告)号：US07675724B2

公开(公告)日：2010-03-09

申请号：US12114485

申请日：2008-05-02

Applicant: Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

IPC: H02H3/22

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

Abstract translation: 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。

公开(公告)号：US20070188952A1

公开(公告)日：2007-08-16

申请号：US11618674

申请日：2006-12-29

Applicant: Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

IPC: G01S13/08 ,  H02H9/00

CPC classification number: H01L27/0248 ,  H03K17/0822

Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

Abstract translation: 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

公开(公告)号：US07663853B2

公开(公告)日：2010-02-16

申请号：US11618674

申请日：2006-12-29

Applicant: Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

IPC: H02H7/00

CPC classification number: H01L27/0248 ,  H03K17/0822

Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

Abstract translation: 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

公开(公告)号：US07253999B2

公开(公告)日：2007-08-07

申请号：US10446049

申请日：2003-05-28

Applicant: Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

IPC: H02H9/00

CPC classification number: H01L27/0248 ,  H03K17/0822

Abstract: An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

Abstract translation: 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

公开(公告)号：US06838908B2

公开(公告)日：2005-01-04

申请号：US10400873

申请日：2003-03-28

Applicant: Ming-Dou Ker ,  Che-Hao Chuang ,  Kuo-Chung Lee ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Che-Hao Chuang ,  Kuo-Chung Lee ,  Hsin-Chin Jiang

IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC classification number: H03K19/00361

Abstract: A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.

Abstract translation: 提供了一种混合电压I / O缓冲电路，其防止通过驱动级PMOS晶体管的泄漏。 缓冲电路具有第一部分，其防止通过晶体管的寄生二极管的泄漏;以及第二部分，当第二部分通过具有高于电源电压的电压电平的焊盘上的信号导通晶体管时，防止漏电流通过晶体管 的缓冲电路。 当焊盘在其上具有高电压信号时，缓冲电路向PMOS晶体管的栅极和衬底端子提供大致等于高电压信号的偏压，并且提供大致等于缓冲电路的电源电压的偏置， 当焊盘在其上具有低电压信号时，PMOS晶体管的栅极和衬底。

公开(公告)号：US06576974B1

公开(公告)日：2003-06-10

申请号：US10094814

申请日：2002-03-12

Applicant: Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2900

CPC classification number: H01L29/7317 ,  H01L27/0259 ,  Y10S977/936

Abstract: An integrated circuit device receiving signals from a signal pad that includes at least one silicon bipolar junction transistor responsive to the signals from the signal pad for providing electrostatic discharge protection, and a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one silicon bipolar junction transistor, wherein the at least one silicon bipolar junction transistor includes an emitter, collector and base formed in a single silicon layer and isolated from a substrate of the integrated circuit device, and wherein the base is coupled to the detection circuit to receive the bias voltage.

Abstract translation: 接收来自信号焊盘的信号的集成电路装置，其响应于来自信号焊盘的用于提供静电放电保护的信号而包括至少一个硅双极结型晶体管，以及检测电路，用于检测来自信号焊盘的信号并提供偏置电压 到所述至少一个硅双极结型晶体管，其中所述至少一个硅双极结型晶体管包括形成在单个硅层中并与所述集成电路器件的衬底隔离的发射极，集电极和基极，并且其中所述基极耦合到 检测电路接收偏置电压。

公开(公告)号：USRE43215E1

公开(公告)日：2012-02-28

申请号：US11598154

申请日：2006-11-09

Applicant: Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

IPC: H01L23/62

CPC classification number: H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

Abstract translation: 本发明涉及一种具有改进的ESD稳健性的静电放电（ESD）器件，用于保护I / O单元库中的输出缓冲器。 根据本发明的ESD装置使用新颖的I / O单元布局结构来实现导通抑制方法，其通过添加拾取扩散区域和/或改变来降低ESD保护MOS晶体管的导通速度 通道长度在布局结构中。