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公开(公告)号：US07675724B2
公开(公告)日：2010-03-09
申请号：US12114485
申请日：2008-05-02
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。
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公开(公告)号：US07394630B2
公开(公告)日：2008-07-01
申请号：US10268756
申请日：2002-10-11
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。
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公开(公告)号：US20090009916A1
公开(公告)日：2009-01-08
申请号：US12114485
申请日：2008-05-02
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。
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公开(公告)号：US20090135533A1
公开(公告)日：2009-05-28
申请号：US11987222
申请日：2007-11-28
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。 第一端耦合到触发单元的输入端。 在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。
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5.发明申请公开(公告)号：US20090009229A1
公开(公告)日：2009-01-08
申请号：US11773966
申请日：2007-07-06
IPC分类号： H03L5/00
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译： 本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。 接口电路包括第一晶体管，体电压发生器模块和偏置模块。 第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。 大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。 偏置模块耦合到第一晶体管的栅极。 偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。
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公开(公告)号：US20070188952A1
公开(公告)日：2007-08-16
申请号：US11618674
申请日：2006-12-29
申请人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
摘要翻译： 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。
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7.发明授权公开(公告)号：US08829775B2
公开(公告)日：2014-09-09
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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8.发明申请公开(公告)号：US20130221834A1
公开(公告)日：2013-08-29
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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公开(公告)号：US08116049B2
公开(公告)日：2012-02-14
申请号：US12625449
申请日：2009-11-24
申请人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
发明人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H02H1/0007
摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.
摘要翻译： 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。 晶体管与电容器耦合，检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此，形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。
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公开(公告)号：US07915638B2
公开(公告)日：2011-03-29
申请号：US12113912
申请日：2008-05-01
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。
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