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    Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithm
    3.
    发明申请
    Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithm 审中-公开
    在全局lanczos算法中减少多输入多输出（MIMO）互连电路系统的方法

    公开(公告)号：US20080126028A1

    公开(公告)日：2008-05-29

    申请号：US11527117

    申请日：2006-09-26

    申请人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    发明人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036 ,  H04L5/20

    摘要： A method of reducing a MIMO interconnect circuit system in a global Lanczos algorithm is used for estimation of the error margin between the original model and the reduced model of MIMO circuit system. In the algorithm, a projection matrix and then a circuit of declining order system are given. A turbulence system being added to the original system, the transfer function union is completely identical to the reduced system union given in the algorithm. It proves that the union of preceding 2q order of the transfer function of reduced system may be surely corresponding to that of original system. It is deduced from the turbulence system added to the original system that the union of preceding 2q order is equal to that of reduced system. In this invention, the algorithm is the basis of determination of the reduced circuit order in a model reduction algorithm a Krylov subspace.

    摘要翻译： 在全局Lanczos算法中减少MIMO互连电路系统的方法用于估计原始模型和MIMO电路系统的简化模型之间的误差容限。 在算法中，给出了一个投影矩阵，然后给出了一个下降阶系统的电路。 湍流系统被添加到原始系统中，传递函数联合与算法中给定的简化系统联合完全相同。 证明了减少系统传递函数的前2q次序的并集可以肯定地对应于原系统的传递函数。 从原始系统的湍流系统推导出，前2q级联合与减少系统的联合相等。 在本发明中，该算法是在Krylov子空间中的模型简化算法中确定简化电路顺序的基础。

    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions
    4.
    发明申请
    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions 有权
    用于RLC互连的伴随网络技术的概括模型级减少

    公开(公告)号：US20060100831A1

    公开(公告)日：2006-05-11

    申请号：US10982668

    申请日：2004-11-05

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036

    摘要： The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This paper extends this technique for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposal method.

    摘要翻译： 伴随网络减少技术已被证明可以减少构造一致性变换矩阵的计算复杂度的50％。 该方法适用于分析RLC互连电路的特殊多端口驱动点阻抗。 本文对RLC互连的一般情况进行了扩展。 还研究了常规方法和提出的方法之间的比较研究。 实验结果将表明提案方法的准确性和效率。

    Method of estimating crosstalk noise in lumped RLC coupled interconnects
    5.
    发明申请
    Method of estimating crosstalk noise in lumped RLC coupled interconnects 失效
    估计集中RLC耦合互连中串扰噪声的方法

    公开(公告)号：US20050278668A1

    公开(公告)日：2005-12-15

    申请号：US10853854

    申请日：2004-05-25

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects is provided. In the invention, high-speed VLSI interconnects are modeled as lumped RLC coupled trees. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

    摘要翻译： 提供了一种用于有效估计高速VLSI互连的串扰噪声的方法。 在本发明中，高速VLSI互连被建模为集中RLC耦合的树。 可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。 考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。 此外，每个节点的电压矩的分析公式将被明确推导出来。 可以有效地实现这些公式用于串扰估计。

    Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm
    6.
    发明申请
    Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm 失效
    通过非对称Lanczos算法确定高速VLSI低阶互连的方法

    公开(公告)号：US20060282799A1

    公开(公告)日：2006-12-14

    申请号：US11148086

    申请日：2005-06-08

    申请人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    发明人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Two-sided projection-based model reductions has become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered as a stopping criteria to terminate the non-symmetric Lanczos iteration process. Furthermore, it can be found that the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves at most rank-2 modification at the previous step of the non-symmetric algorithm. The information of stopping criteria will provide a guideline for the order selection scheme used in the Lanczos model-order reduction algorithm.

    摘要翻译： 基于双面投影的模型降低已经成为VLSI设计中高效互连建模和仿真的必要条件。 为了选择真正反映原始互连的基本动力学的简化系统的顺序，传递函数的简化模型的要素可以被认为是终止非对称Lanczos迭代过程的停止标准。 此外，可以发现近似传递函数也可以表示为具有一些附加扰动的原始互连模型。 扰动矩阵在非对称算法的前一步骤中仅涉及至多二等级修改。 停止标准的信息将为Lanczos模型 - 订单减少算法中使用的订单选择方案提供指导。

    Method of estimating crosstalk noise in lumped RLC coupled interconnects
    7.
    发明授权
    Method of estimating crosstalk noise in lumped RLC coupled interconnects 失效
    估计集中RLC耦合互连中串扰噪声的方法

    公开(公告)号：US07124381B2

    公开(公告)日：2006-10-17

    申请号：US10853854

    申请日：2004-05-25

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects models high-speed VLSI interconnects as lumped RLG coupled frees. An inductive crosstalk noise waveform can be accurately estimated in an efficient manner using a linear time moment computation technique in conjunction with a projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived taking into consideration of both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for use in crosstalk estimations.

    摘要翻译： 高效VLSI互连的串扰噪声的有效估计方法是将高速VLSI互连模型作为集中的RLG耦合释放模型。 可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。 考虑到自感和互感两者，导出耦合RC树的力矩计算的递归公式。 此外，每个节点的电压矩的分析公式将被明确推导出来。 这些公式可以有效地实现用于串扰估计。

    Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops
    8.
    发明申请
    Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops 有权
    高速VLSI与电阻环R（L）C互连中的时刻计算方法

    公开(公告)号：US20060015832A1

    公开(公告)日：2006-01-19

    申请号：US10889795

    申请日：2004-07-13

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F17/50 ,  G06F17/10

    CPC分类号： G06F17/5036

    摘要： A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results have demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

    摘要翻译： 提出了一种具有多个电阻环路的通用集总R（L）C互连电路的新时刻计算技术。 集中R（L）C网络使用撕裂概念可以划分为生成树和几个电阻链路。 来自每个树的网络时刻的贡献和相应的链接可以独立确定。 通过组合常规力矩计算算法和减少二阶决策图（ROBDD），提出的方法可以有效地计算系统时间。 实验结果表明，所提出的方法确实可以获得准确的时刻，并且比常规方法更有效。

    Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design
    9.
    发明授权
    Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design 失效
    在集成电路设计过程中搜索静电放电的路径的方法

    公开(公告)号：US07398499B2

    公开(公告)日：2008-07-08

    申请号：US11440349

    申请日：2006-05-24

    申请人： Ming-Hong Lai ,  Chao-Yi Cho ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Ming-Hong Lai ,  Chao-Yi Cho ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06G17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. −1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.

    摘要翻译： 公开了一种在集成电路（IC）设计开始时检测易受静电放电（ESD）的路径的方法，其包括电路扩展算法，矩阵闭合算法和超级节点算法。 找到的路径需要满足包括（a）它们从晶体管的栅极连接到其源极或漏极的条件，以及（b）每个路径的头节点和尾节点是顶级的引脚 的IC。 -1 / / 1矩阵乘法由电路扩展算法和矩阵闭合算法两者采用，以便在多个矩阵自乘之后获得节点连接的结果。

    Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design
    10.
    发明申请
    Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design 失效
    在集成电路设计过程中搜索静电放电的路径的方法

    公开(公告)号：US20070277138A1

    公开(公告)日：2007-11-29

    申请号：US11440349

    申请日：2006-05-24

    申请人： Ming-Hong Lai ,  Chao-Yi Cho ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Ming-Hong Lai ,  Chao-Yi Cho ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： A new method of searching paths that are suffering ESD is proposed in this invention, improving the design flow of a VLSI circuit and reducing the cost of designing the ESD circuits in a whole chip, comprising three parts, the circuit flattening, the closure algorithm, and the supernode algorithm. The objective is to find the paths satisfying the following two constraints: (1) only one edge connected to the gate pin and the source (or drain) pin is allowed; (2) only the head-node and the tail-node in a path could be the pin of top-level circuit. Two algorithms in this invention are the closure algorithm that uses the closure property in the −1/0/1 matrix multiplication so that the connective property of nodes can be observed after several matrix self-multiplication, and the supernode algorithm.

    摘要翻译： 本发明提出了一种新型的ESD检测路径，提高了VLSI电路的设计流程，降低了设计整个芯片ESD电路的成本，包括三部分：电路平坦化，闭合算法， 和超节点算法。 目的是找到满足以下两个约束的路径：（1）允许仅连接到栅极引脚和源极（或漏极）引脚的一个边沿; （2）路径中的头节点和尾节点只能是顶层电路的引脚。 本发明中的两种算法是使用-1 / 0/1矩阵乘法中的闭合属性的闭合算法，使得可以在几个矩阵自乘以及超节点算法之后观察节点的连接属性。