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    Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithm
    2.
    发明申请
    Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithm 审中-公开
    在全局lanczos算法中减少多输入多输出（MIMO）互连电路系统的方法

    公开(公告)号：US20080126028A1

    公开(公告)日：2008-05-29

    申请号：US11527117

    申请日：2006-09-26

    申请人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    发明人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036 ,  H04L5/20

    摘要： A method of reducing a MIMO interconnect circuit system in a global Lanczos algorithm is used for estimation of the error margin between the original model and the reduced model of MIMO circuit system. In the algorithm, a projection matrix and then a circuit of declining order system are given. A turbulence system being added to the original system, the transfer function union is completely identical to the reduced system union given in the algorithm. It proves that the union of preceding 2q order of the transfer function of reduced system may be surely corresponding to that of original system. It is deduced from the turbulence system added to the original system that the union of preceding 2q order is equal to that of reduced system. In this invention, the algorithm is the basis of determination of the reduced circuit order in a model reduction algorithm a Krylov subspace.

    摘要翻译： 在全局Lanczos算法中减少MIMO互连电路系统的方法用于估计原始模型和MIMO电路系统的简化模型之间的误差容限。 在算法中，给出了一个投影矩阵，然后给出了一个下降阶系统的电路。 湍流系统被添加到原始系统中，传递函数联合与算法中给定的简化系统联合完全相同。 证明了减少系统传递函数的前2q次序的并集可以肯定地对应于原系统的传递函数。 从原始系统的湍流系统推导出，前2q级联合与减少系统的联合相等。 在本发明中，该算法是在Krylov子空间中的模型简化算法中确定简化电路顺序的基础。

    Method and apparatus for model-order reduction and sensitivity analysis
    4.
    发明授权
    Method and apparatus for model-order reduction and sensitivity analysis 有权
    用于模型顺序降低和灵敏度分析的方法和装置

    公开(公告)号：US07216309B2

    公开(公告)日：2007-05-08

    申请号：US10839953

    申请日：2004-05-06

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F17/16 ,  G06F17/17

    CPC分类号： G06F17/5036

    摘要： Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

    摘要翻译： 通过使用经修改的节点分析公式的对称性来减少用于建模VLSI互连电路的计算机时间。 该建模使用修改的节点分析矩阵，然后应用Krylov子空间矩阵来构造一致变换矩阵以生成VLSI的简化阶模型。

    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions
    5.
    发明申请
    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions 有权
    用于RLC互连的伴随网络技术的概括模型级减少

    公开(公告)号：US20060100831A1

    公开(公告)日：2006-05-11

    申请号：US10982668

    申请日：2004-11-05

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036

    摘要： The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This paper extends this technique for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposal method.

    摘要翻译： 伴随网络减少技术已被证明可以减少构造一致性变换矩阵的计算复杂度的50％。 该方法适用于分析RLC互连电路的特殊多端口驱动点阻抗。 本文对RLC互连的一般情况进行了扩展。 还研究了常规方法和提出的方法之间的比较研究。 实验结果将表明提案方法的准确性和效率。

    Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration
    6.
    发明申请
    Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration 有权
    用于快速选择插入到时钟树中的用于高速大规模集成的缓冲器的类型的方法和装置

    公开(公告)号：US20060010414A1

    公开(公告)日：2006-01-12

    申请号：US10889510

    申请日：2004-07-12

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/62

    摘要： A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, inserted buffers locations information, wires electrical parameters and buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, clock delay and clock skew can be obtained. Finally using the proposed method, a modified clock tree netlist which satisfying the timing specifications can be constructed.

    摘要翻译： 公开了一种用于快速选择插入时钟树中用于高速VLSI设计的缓冲器类型的方法和装置。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保最小化时钟延迟并满足时钟偏移约束。 给定时钟树网表，插入缓冲区位置信息，电线参数和缓冲定时库，可以首先计算时钟树的组件延迟（缓冲延迟和线延迟）。 然后，对于每个I / O引脚，可以获得路径延迟，时钟延迟和时钟偏移。 最后使用所提出的方法，可以构建满足定时规范的修改的时钟树网表。

    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions
    8.
    发明授权
    Generalizations of adjoint networks techniques for RLC interconnects model-order reductions 有权
    用于RLC互连的伴随网络技术的概括模型级减少

    公开(公告)号：US07797140B2

    公开(公告)日：2010-09-14

    申请号：US10982668

    申请日：2004-11-05

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Ming-Hong Lai

    IPC分类号： G06F7/60 ,  G06F17/10

    CPC分类号： G06F17/5036

    摘要： The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This technique is extended for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposed method.

    摘要翻译： 伴随网络减少技术已被证明可以减少构造一致性变换矩阵的计算复杂度的50％。 该方法适用于分析RLC互连电路的特殊多端口驱动点阻抗。 对于RLC互连的一般情况，该技术被扩展。 还研究了常规方法和提出的方法之间的比较研究。 实验结果将证明所提方法的准确性和效率。

    Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm
    9.
    发明授权
    Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm 失效
    通过非对称Lanczos算法确定高速VLSI低阶互连的方法

    公开(公告)号：US07509243B2

    公开(公告)日：2009-03-24

    申请号：US11148086

    申请日：2005-06-08

    申请人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    发明人： Chia-Chi Chu ,  Ming-Hong Lai ,  Wu-Shiung Feng

    IPC分类号： G06F17/10 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： Two-sided projection-based model reductions have become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered as a stopping criteria to terminate the non-symmetric Lanczos iteration process. Furthermore, the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves at most a rank-2 modification at the previous step of the non-symmetric algorithm. The information of stopping criteria will provide a guideline for the order selection scheme used in the Lanczos model-order reduction algorithm.

    摘要翻译： 基于双面投影的模型降低已经成为VLSI设计中高效互连建模和仿真的必要条件。 为了选择真正反映原始互连的基本动力学的简化系统的顺序，传递函数的简化模型的要素可以被认为是终止非对称Lanczos迭代过程的停止标准。 此外，近似传递函数也可以表示为具有一些附加扰动的原始互连模型。 扰动矩阵在非对称算法的前一步骤中最多仅涉及等级-2修改。 停止标准的信息将为Lanczos模型 - 订单减少算法中使用的订单选择方案提供指导。

    Interconnect model-order reduction method
    10.
    发明授权
    Interconnect model-order reduction method 失效
    互连模型阶降序法

    公开(公告)号：US07437689B2

    公开(公告)日：2008-10-14

    申请号：US11199026

    申请日：2005-08-08

    申请人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    发明人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

    摘要翻译： 互连模型级降低方法通过使用基于迭代的Arnoldi算法将纳米级半导体互连网络作为原始互连网络减少。 该方法基于投影方法进行，并且已经成为有效的互连建模和模拟的必要条件。 为了选择可以有效地反映原始互连网络的基本动力学的简化模型的顺序，原始互连网络的传递函数与简化的互连模型之间的残差可以被认为是在确定迭代过程中的参考 应该结束，这里得到的残差的解析表达式。 此外，还原互连模型的近似传递函数也可以表示为原始互连模型和一些附加扰动的相加。 扰动矩阵仅与Arnoldi算法前一步的合成矢量有关。 因此，剩余误差信息可以作为Krylov子空间模型顺序算法中使用的顺序选择方案的参考。